|
[1] K. Khare, R. Kar, D. Mandal, and S.P. Ghoshal, “Analysis of Leakage Current and Leakage Power Reduction during Write operation in CMOS SRAM Cell,” in ICCSP, pp. 523-527, 2014. [2] P. Stanley-Marbell, V. C. Cabezas, and R. P. Luijten, “Pinned to the walls—Impact of packaging and application properties on the memory and power walls,” inProc. Int. Symp. Low Power Electron. Design, pp. 51–56, Aug. 2011. [3] Arnab Raha, Akhilesh Jaiswal, Syed Shakib Sarwar, Vijay Raghunathan, Kaushik Roy, “Designing Energy- Efficient Intermittently Powered Systems Using Spin-Hall-Effect-Based Nonvolatile SRAM,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-14, 2017. [4] Fengying Sun, Kecheng Ji, Ming Ling, Longxing Shi, “A trace-driven analytical model with less profiling overhead for DRAM access latencies,”2017 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), pp. 1-6, 2017. [5] Wonchan Kim, Joongsik Kih, Gyudong Kim, Sanghun Jung, Gijung Ahn, “An experimental high-density DRAM cell with a built-in gain stage,” IEEE Journal of Solid-State Circuits, vol. 29, pp. 978-981,1994. [6] T. Tanaka; E. Yoshida; T. Miyashita, “Scalability study on a capacitorless 1T-DRAM: from single-gate PD-SOI to double-gate FinDRAM”, IEDM Technical Digest. IEEE International Electron Devices Meeting, pp. 919-922, 2004. [7] G. Atwood, “Future Directions and Challenges for ETox Flash Memory Scaling”, Device and Materials Reliability, IEEE Transactions on, vol. 4, pp.301-305, 2004. [8] S. Shukuri, S. Shimizu, N. Ajika, T. Ogura, M. Mihara, Y. Kawajiri, K. Kobayashi, and M. Nakashima , "A 10k-Cycling Reliable 90nm LogicNVM "eCFlash" (Embedded CMOS Flash) Technology," 2011 3rd IEEE Memory Workshop (IMW), Monterey, CA, pp. 1-2, 2011. [9] Jaehoon Jang, Han-Soo Kim, Wonseok Cho, Hoosung Cho, Jinho Kim, Sun Il Shim, Younggoan, Jae-Hun Jeong, Byoung-Keun Son, Dong Woo Kim; Kihyun, Jae-Joo Shim, Jin Soo Lim, Kyoung-Hoon Kim, Su Youn Yi, Ju-Young Lim, Dewill Chung, Hui-Chang Moon, Sungmin Hwang, “Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory,” 2009 Symposium on VLSI Technology, pp.192-193, 2009. [10] K. Kim, J. H. Choi, J. Choi, and H.-S. Jeong, “The future prospect of nonvolatile memory,” IEEE VLSI-TSA International Symposium on, pp.88,94, 25-27, April 2005. [11] P. J. Wright, and K. C. Saraswat, “Thickness Limitations of SiO2 Gate Dielectrics for MOS ULSI,” in IEEE, Trans. Electron Devices, vol. 37, no. 8, pp. 1884-1892, 1990. [12] Chen, Y.S., Lee, H.Y., “ Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity,” in IEDM, pp.105-108, 2009. [13] Guodong Wang, Xiaolian Liu, Wei Wang, “Solution Processed Organic Transistor Nonvolatile Memory with a Floating-gate of Carbon Nanotubes,” IEEE Electron Device Letters, pp. 1, 2017. [14] B. Wang, H. Nguyen, Y. Ma and R. Paulsen, “Highly Reliable 90-nm Logic Multitime Programmable NVM Cells Using Novel Work-Function-Engineered Tunneling Devices,” in IEEE Transactions on Electron Devices, vol. 54, no. 9, pp. 2526-2530 , Sept. 2007. [15] C.Y. Mei, W.C. Shen, Y. D. Chih, Y. C. King and C. J. Lin, “28nmhigh-k metal gate RRAM with fully compatibleCMOS logicprocesses,” 2013 International Symposium on VLSI Technology,Systems and Application (VLSI-TSA), Hsinchu, pp. 1-2, 2013. [16] M. Tsoi, A. G. M. Jansen, “Excitation of a Magnetic Multilayer by an Electric Current”, in Phys. Rev. Lett. 80, 4281–4284, 1998. [17] C.J. Lin, S.H. Kang, “45nm Low Power CMOS Logic Compatible Embedded STT MRAM Utilizing a Reverse-Connection 1T/1MTJ Cell”, in IEDM, pp.279-282, 2009. [18] D. Halupka, S. Huda, W. Song, A. Sheikholeslami, K. Tsunoda, C.Yoshida, and M. Aoki, “Negative-resistance read and write schemes for STT-MRAMin 0.13μm CMOS”, Solid-State Circuits Conference Digest og Technical Papers (ISSCC), 2010 IEEE International, pp.256-257, 7-11 Feb.2010. [19] K.-T. Nam, S. C. Oh, “Switching Properties in Spin Transfer Torque MRAM with sub-50nm MTJ size,” in NVMTS, pp.49-51, 2006. [20] Jeong-Heon Park, Y. Kim, W. C. Lim, J. H. Kim, S. H. Park, J. H. Kim, W. Kim, K. W. Kim, J. H. Jeong, K. S. Kim, H. Kim, Y. J. Lee, S. C. Oh, J. E. Lee, S. O. Park, S. Watts, D. Apalkov, “Enhancement of data retention and write current scaling for sub-20nm STT-MRAM by utilizing dual interfaces for perpendicular magnetic anisotropy,” 2012 Symposium on VLSI Technology (VLSIT), pp.57-58, 2012. [21] Balla, P.e. and Antoniou, A., “Low Power Dissipation MOS Ternary Logic Family,” IEEE J. Solid-State Circuits, Vol. 19, No. 5, pp. 739-749, Oct, 1984. [22] Heung, A. and Mouftah, H.T., “Depletionl Enhancement CMOS for a Lower Power Family of Three-valued Logic Circuits,” IEEE J. Solid-State Circuits, Vol. 20, No. 2, pp. 609-616, Apr, 1985. [23] G. Servalli, “A 45nm Generation Phase Change Memory Technology”, in IEDM, pp.113-116, 2009. [24] G. F. Close, U. Frey, J. Morrish, R. Jordan, S. Lewis, T. Maffitt, M.Breitwisch, C. Hagleitner, C. Lam, and E. Eleftheriou, “A 512Mb phasechange memory (PCM) in 90nm CMOS achieving 2b/cell”, VLSI Circuits(VLSIC), 2011 Symposium on, pp.202-203, 15-17 June 2011. [25] Lee, H.Y., Chen, P.S., “Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM”, in IEDM, 2008.
[26] I.S. Park, K.R. Kim, S. Lee, J. Ahn,”Resistance switching characteristics fornonvolatile memory operation of binarymetal oxides”, in Jpn. J. Appl. Phys., vol. 46,pp. 2172–2174, Apr. 2007. [27] K.P.Chang, W.C.Chien, Y.C.Chen, E.K.Lai, S.C.Tsai, ,S.H.Hsieh, “Low-voltage and fast-speed forming process of tungsten oxide resistive memory,” in Extended Abstracts Int. Conf. Solid State Devices Mater., Tsukuba ,pp. 1168–1169, Sep .2008. [28] S. Karg, G. I. Meijer, D. Widmer, R. Stutz, J. G. Bednorz, and Ch. Rettner, “Nanoscale Resistive Memory Device Using SrTiO3 Films”, Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE, pp.68-70, 26-30 Aug, 2007. [29] P. Huang. X. Y. Liu, B. Chen, H. T. Li, Y. J. Wang, Y. X. Deng, K. L. Wei, L. Zeng, B. Gao, G. Du, X. Zhang, and J. F. Kang, “A Physics-Based Compact Model of Metal-Oxide-Based RRAM DC and AC Operations,” in IEEE Trans. Electronic Devices, vol. 60, no. 12, pp. 4090-4097, 2013. [30] Y.W. Chin, S.E.Chen, M.C. Hsieh, T.S. Chang, C.J. Lin, Y.C. King, “Point twin-bit RRAM in 3D interweaved cross-point array by Cu BEOL process”, in IEDM, Dec. 2014. [31] Wen Chao Shen, Chin Yu Mei, Y. -D. Chih, Shyh-Shyuan Sheu, Ming-Jinn Tsai, Ya-Chin King, Chrong Jung Lin, “High-K metal gate contact RRAM (CRRAM) in pure 28nm CMOS logic process”, 2012 International Electron Devices Meeting, pp. 31.6.1-31.6.4, 2012. [32] Ugo Russo et al., “Self-Accelerated Thermal Dissolution Model for Reset Programming in Unipolar Resistive-Switching Memory (RRAM) Devices,”IEEE Transactions on Electron Device, Vol. 56, no. 2, Feb 2009. [33] Bin Gao, Bing Sun, “Unified Physical Model of Bipolar oxide-Based Resistive Switching Memory” in EDL, Volume: 30 , Issue: 12, 2009. [34] B. Gao, B. Sun, H. Zhang, L. Liu, X. Liu, R. Han, J. Kang, B. Yu, “Unified Physical Model of Bipolar Oxide-Based Resistive Switching Memory”, in EDL, Vol.30, No.12, pp.1326-1328, 2009. [35] Chun-Chieh Lin, Chih-Yang Lin,” Voltage-Polarity-Independent and High-Speed Resistive Switching Properties of V-Doped SrZrO3 Thin Films”, in TED Volume 54 , Issue 12, 2007. [36] M.J. Lee, Y. Park, B.S. Kang, S.E. Ahn, C. Lee, K. Kim, W. Xianyu, G. Stefanovich, J.H. Lee, S.J. Chung, Y.H. Kim, C.S. Lee, J. B. Park , I.G. Baek, I.K. Yoo, “2-stack ID-IR Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications”, in IEDM, pp.771-774, 2007. [37] E. Linn, R. Rosezin, C. Kügeler and RainerWaser, “Complementary resistive switches for passive nanocrossbar memories,” in Nat. Mater., vol.9, no.5, pp.403-406, 2010. [38] S. Ambrogio, S. Balatti, D. Ielmini, and D. C. Gilmer, “Analytical modelling and leakage optimization in complementary resistive switch (CRS)crossbar arrays”, Solid State Device Research Conference (ESSDERC), 2014 44th European, pp.242-245, 22-26 Sept. 2014. [39] C.-L. Lo, M.-C. Chen, J.-J. Huang, and T.-H. Hou, “On the Potential of CRS, 1D1R, and 1S1R Crossbar RRAM for Storage-Class Memory”, VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on, pp.1-4, 22-24 , Apr. 2013. [40] Y. Li, W. Chen, W. Lu, and R. Jha,“Impact of coupling capacitance on read operation of RRAM devices in 1D1R crossbar architectures”, Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on, pp.989-992, 3-6 Aug. 2014. [41] M.-J. Lee, Y. Park, B.-S. Kang, S.-E. Ahn, C. Lee, K. Kim, W. Xianyu, G. Stefanovich, J.-H. Lee, S.-J. Chung, Y.-H. Kim, C.-S. Lee, J.-B. Park , I.-G. Baek and I.-K. Yoo, “2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications”, Electron Devices Meeting, 2007. IEDM 2007. IEEE International, pp.771-774, 10-12 Dec. 2007. [42] Hyunjun Sim, Hyejung Choi,“Excellent resistance switching characteristics of Pt/SrTiO¬3 schottky junction for multi-bit nonvolatile memory application”, in IEDM pp.758-761, 2005. [43] Bin Jiao, Ning Deng, Jie Yu, Yue Bai, Minghao Wu, Ye Zhang; He Qian, Huaqiang Wu, “Resisitive switching variability study on 1T1R AlOx/WOx-based RRAM array,” 2013 IEEE International Conference of Electron Devices and Solid-state Circuits, pp. 1-2, 2013.
[44] Te-Liang Lee, Yi-Hung Tsai, Wun-Jie Lin, Hsiao-Lan Yang; Chiu-Wang Lien, Chrong Jung Lin, Ya-Chin King, “A New Differential P-Channel Logic-Compatible Multiple-Time Programmable (MTP) Memory Cell With Self-Recovery Operation”, IEEE Electron Device Letters, Vol. 32, pp.587-589.
|