此論文分析將調變絕緣層介電係數降低表面電場(Dielectric RESURF)應用於高壓鰭式場效電晶體。此高壓鰭式場效電晶體採14奈米鰭式場效電晶體製程步驟做為參考並結合電腦模擬軟體(TCAD)建立高壓鰭式場效電晶體結構。針對元件的電特性、崩潰電壓、特定導通電阻(Specific on-resistance，縮寫Ron,sp)做進一步的分析與討論。
本文提出的鰭式場效電晶體，以閘極長度為0.1μm，漂移區為1.0μm，絕緣層寬度為0.033μm、深度為0.1μm作為基準結構，並在電特性上與平面式場效電晶體做比較。為了取得漂移區離子佈植的最佳劑量，必須在崩潰電壓與Ron,sp之間作抉擇。本文探討Dielectric RESURF技術並證實增加絕緣層寬度或提高絕緣層介電係數可以提升漂移區離子佈植的最佳劑量。當絕緣層寬度從33nm增加至81nm時，漂移區離子佈植的最佳劑量從4.2x1012cm-2提升至6.9 x1012 cm-2。此外，本文也針對提高絕緣層的介電係數進行探討，當絕緣層介電係數從3.9(SiO2)提高至86(TiO2)時可以提升高壓鰭式場效電晶體的崩潰電壓與降低Ron,sp。在高壓鰭式場效電晶體結合Dielectric RESURF技術下，使用高介電係數絕緣層(K=86)之高壓鰭式場效電晶體的最高崩潰電壓為32.23V，最高FOM值為19536 V2/mΩ-cm2，相較使用低介電係數絕緣層(K=3.9)之高壓鰭式場效電晶體，在最高崩潰電壓上提高24.6%，最高FOM值提高154%。

In this thesis, the analysis of dielectric RESURF implemented in high-voltage FinFETs has been studied. The high-voltage FinFET structure with a typical 14nm FinFET fabrication process flow has been established by using Technology Computer Aided Design (TCAD) simulation, in order to discuss the electrical characteristics of this device including breakdown voltage and specific on-resistance (Ron,sp).
For the FinFET structure under study, the gate length is 0.1μm and the drift region length is 1.0μm. Typical STI width(WSTI) is 0.033μm, and typical STI thickness(TSTI) is 0.1μm. The FinFET is compared with a planar MOSFET in electrical characteristics for finding the optimized dose for the drift region implant for a better tradeoff between breakdown voltage and Ron,sp. The concept of dielectric RESURF is explored, and it was found that a higher optimal dose for drift region implant can be achieved by either increasing the width of the STI or by adopting a higher dielectric constant. As the WSTI increased from 33nm to 81nm, the optimal dose for drift region is increased from 4.2x1012cm-2 to 6.9x1012 cm-2. Furthermore, the effect of dielectric constant of STI is also discussed. As the dielectric constant of STI increased from 3.9(SiO2) to 86(TiO2), the breakdown voltage can be increased, and the specific on-resistance can be reduced. With dielectric RESURF in high-voltage FinFETs, the maximum breakdown voltage reaches 32.23V when a High-k (k=86) dielectric is used, and the maximum FOM reaches 19536 V2/mΩ-cm2. The maximum breakdown voltage increased voltage by 24.6%, and the maximum FOM increased value by 154% compared to a Low-k one (k=3.9) case.

摘要 I
Abstract II
目錄 III
圖目錄 V
表目錄 IX
第一章 序論 1
1.1研究動機 1
1.2橫向擴散場效電晶體簡介 2
1.2.1 降低表面電場技術(RESURF)-文獻回顧 3
1.2.2絕緣介電質降低表面電場技術(Dielectric RESURF) 6
1.3鰭式場效電晶體發展與介紹 9
1.3.1 絕緣矽基板、全矽基板鰭式場效電晶體簡介 10
1.3.2 短通道效應簡介 13
1.3.3汲極延伸鰭式場效電晶體 16
1.4論文架構 18
第二章 元件結構與製程流程 19
2.1元件結構 19
2.2製程流程 23
第三章 模擬結果與討論分析 38
3.1閘極長度對於元件的影響 38
3.1.1設計閘極長度 38
3.1.2比較平面式場效電晶體與鰭式場效電晶體的電特性 44
3.2調變STI對於HV-FinFET耐壓能力的影響 55
3.2.1調變STI寬度 55
3.2.2調變STI介電係數 59
3.2.3 調變STI深度 68
第四章 結論與未來工作 76
4.1結論 76
4.2未來工作 76
參考文獻 77

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