最近幾年以來，因為雲端計算及多媒體應用使得對於寬頻電路之需求不斷地增加，在超高速有線傳輸中，光纖通訊有著低損耗、高頻寬、低電磁干擾及低串音之特性，所以越來越多的團隊投入使得光纖通訊系統變成一之熱門之研究主題。在目前的市場中，25-Gb/s 的光纖通訊產品為主流，而下一代的研究目標即為400 Gb/s之光纖通訊系統，所以在此論文中，我們將專注在50-Gbaud/s轉阻放大器的設計上。
第二章中，我們使用180 nm CMOS製程設計一10-Gb/s轉阻放大器，利用RGC架構來當作轉阻放大器之輸入級，可以得到較低之輸入阻抗進而提升整體頻寬。在量測上，可以達到53.7 dBΩ之轉阻增益及14.5 GHz之頻寬，在電性眼圖量測可以量到10-Gb/s的NRZ訊號眼圖。整體電路的功耗為42.7 mW、晶片面積為0.58mm x 0.72mm。
第三章中，我們使用28 nm CMOS製程設計一60-Gb/s轉阻放大器，利用一般共源級放大器疊接一顆電晶體及電阻回授來當作轉阻放大器之輸入級。在量測上，可以達到50.4 dBΩ之轉阻增益及52.5 GHz之頻寬，在電性眼圖量測可以量到60-Gb/s 的NRZ訊號眼圖。整體電路的功耗為27.5mW、晶片面積為0.47mm x 0.78mm。
第四章中，我們使用65 nm CMOS製程設計一50-Gbaud/s轉阻放大器，利用非對稱偏壓之反向式轉阻放大器及電阻回授來當作轉阻放大器之輸入級。在量測上，可以達到50.3 dBΩ之轉阻增益及46.9 GHz之頻寬，在電性眼圖量測可以量到60-Gb/s 的NRZ訊號眼圖，PMA4訊號眼圖則可以量到50-Gbaud/s。整體電路的功耗為86.6 mW、晶片面積為0.6mm x 0.7mm。
第五章中，我們使用SiGe 130 nm BiCMOS製程設計一80-GHz轉阻放大器，利用一般共射級放大器疊接一顆電晶體及電阻回授來當作轉阻放大器之輸入級。在模擬上，可以達到50 dBΩ之轉阻增益及76.5 GHz之頻寬，在電性眼圖量測可量到70-Gbaud/s 的PAM4訊號眼圖。整體電路的功耗為34.5mW、晶片面積為0.43mm x 0.71mm。
第六章中，我們將總結上述章節的工作內容及介紹未來方向，在未來的趨勢裡，雲端計算及多媒體應用使傳輸速度的需求日益增加，可以預期因此400 Gb/s的光纖通訊系統架構已成為一熱門研究題目。

Recently, the continuous growth of demand for broadband service such as cloud computing and multimedia applications makes more and more researches on optical communication systems a very popular research topic because of the characteristics of optical fibers such as low loss, high bandwidth and low EMI. The 25-Gb/s optical communication system is the mainstream on the current market and next generation targets at 400-Gb/s optical communication system, which it is usually divideds into four channels and each channel carries 100-Gb/s data transmission.
Therefore, we focus on 50-Gbaud/s transimpedance amplifier in this thesis.
In chapter 2, a 10-Gb/s transimpedance amplifier in 180 nm CMOS process is presented, using modified RGC current buffer as the input stage and transformer-peaking to obtain a lower input impedance and wider bandwidth. The circuit achieves a transimpedance gain of 53.7 dBΩ and a bandwidth of 14.5 GHz with , and get a clear electrical eye-diagram of 10-Gb/s NRZ signal in time-domain measurements. The power consumption is 42.7 mW with a chip area of 0.58mm x 0.72mm.
In chapter 3, a 60-Gb/s transimpedance amplifier in 28 nm CMOS process is presented, using Common-source amplifier with cascode transistor and shunt-shunt feedback resistor as the input stage. The circuit achieves a transimpedance gain of 50.4 dBΩ and a bandwidth of 52.5 GHz under 27.5 mW power consumption with chip area of 0.47mm x 0.78mm. The measured NRZ signal data-rate is up to 60-Gb/s in the time-domain by electrical eye-diagram measurements.
In chapter 4, a 50-Gbaud/s transimpedance amplifier amplifier in 65nm CMOS process is presented, using asymmetric biasing and sizing inverter with shunt-shunt feedback resistor as the input stage. The circuit achieves a transimpedance gain of 50.3 dBΩ and a bandwidth of 46.9 GHz under 86.6 mW power consumption with chip area 0.6mm x 0.7mm. The measured NRZ signal data-rate is up to 60-Gb/s and the PAM-4 signal data-rate is up to 50-Gbaud/s in the time-domain electrical eye-diagram measurements.
In chapter 5, we propose an 80-GHz transimpedance amplifier in SiGe 130 nm process, using common-emitter amplifier with cascode transistor and shunt-shunt feedback resistor as the input stage. The circuit achieves a transimpedance gain of 50 dBΩ and a bandwidth 76.5 GHz in simulations under 34.5 mW power consumption with a chip area of 0.43mm x 0.71mm. For time domain electrical eye-diagram simulation, the simulated PAM-4 data rate is up to 70 Gbaud/s.
In chapter 6, we will give the conclusion of previous chapters, and introduction to the future works. It is expected that the 400-Gb/s optical system becomes a popular topic because of cloud computing and multimedia.

摘要................................................... i
ABSTRACT............................................... iii
TABLE OF CONTENTS...................................... v
LIST OF FIGURES........................................ viii
LIST OF TABLES......................................... xii
Chapter 1 Introduction........................... 1
1.1 Background and Motivation...................... 1
1.2 Introduction of Optical Communication System... 2
Chapter 2 10-Gb/s RGC Transimpedance Amplifier With Transformer Network.................................... 3
2.1 Introduction of Transimpedance Amplifier....... 3
2.1.1 Considerations of transimpedance amplifier
design......................................... 4
2.2 Topologies of transimpedance amplifier......... 5
2.2.1 Open-loop transimpedance amplifier............. 5
2.2.2 Feedback transimpedance amplifier.............. 6
2.3 Bandwidth Extension Techniques................. 10
2.3.1 Shunt inductive peaking........................ 10
2.3.2 Series inductive peaking....................... 11
2.3.3 Transformer peaking............................ 12
2.3.4 T-coil peaking................................. 14
2.3.5 Asymmetric T-coil paking....................... 15
2.4 Proposed 10-Gb/s Regulated cascode Transimpedance amplifier with Transformer Network..................... 16
2.4.1 Transimpedance amplifier stage................. 17
2.4.2 Post-amplifier stage........................... 18
2.4.3 Buffer stage................................... 18
2.5 Simulation and Measurement Results............. 19
2.5.1 Frequency domain............................... 20
2.5.2 Time domain measurements....................... 21
2.6 Conclusion..................................... 22
Chapter 3 Design of 60-Gb/s Transimpedance Amplifier in 28nm CMOS................................................... 24
3.1 Proposed Transimpedance Amplifier.............. 24
3.1.1 Transimpedance amplifier stage................. 25
3.1.2 Post-amplifier stage........................... 29
3.1.3 Buffer stage................................... 31
3.2 Simulation Results............................. 32
3.2.1 Frequency domain simulations................... 32
3.2.2 Time domain simulations........................ 34
3.3 Measurement Results............................ 35
3.3.1 Frequency domain measurements.................. 36
3.3.2 Time domain measurements....................... 39
3.4 Conclusion..................................... 41
Chapter 4 A 50-Gbaud/s Asymmetric Biasing Inverter-Type TIA in 65nm CMOS........................................... 43
4.1 Introduction of PAM4 Signal.................... 43
4.2 Proposed 50-Gbaud/s TIA........................ 44
4.2.1 Transimpedance amplifier stage................. 44
4.2.2 Post-amplifier stage........................... 46
4.2.3 Buffer stage................................... 47
4.3 Simulation and Measurement results............. 47
4.3.1 Frequency domain............................... 48
4.3.2 Time domain.................................... 52
4.4 Conclusion..................................... 54
Chapter 5 A 80-GHz Transimpedance Amplifier in SiGe 0.13mm BiCMOS Technology...................................... 56
5.1 Introduction of 80-GHz TIA..................... 56
5.2 Proposed 80-GHz TIA............................ 56
5.2.1 Transimpedance amplifier stage................. 57
5.2.2 Post-amplifier stage........................... 60
5.3 Simulation Results............................. 60
5.3.1 Frequency domain simulations................... 60
5.3.2 Time domain simulations........................ 63
5.4 Conclusion..................................... 64
Chapter 6 Conclusion and Future Works............ 66
6.1 Conclusion..................................... 66
6.2 Future Works................................... 67
References............................................. 68

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