現在的電子產品中，不論是手機、相機、電腦等，只要有時序控制的電路，都需要時脈訊號才會運作。時脈訊號的精確度決定了電路的工作穩定度，這些時脈幾乎都是由頻率合成電路(例如PLL, Timing Recovery…等)來產生。而頻率合成電路都需要有一個參考頻率源(Reference Oscillator)因此，如何產生一個穩定頻率的時脈訊號，同時又能配合科技發展的趨勢(低功耗、體積小)，是近年來的重大課題之一。
然而對於需要高精準度的設備而言，大部分的時脈訊號仍是由石英振盪器所產生，主要是因為石英為目前頻率穩定度最高的振盪元件。然而，石英晶體有大面積、高成本、高功率消耗，及無法與CMOS製程做整合等缺點，因此過去幾十年來無論學界專家或公司研究團隊都試圖尋找能替代石英振盪器的方案。
近年來被提出取代石英振盪的方法有MEMS振盪器、FBAR振盪器，及CMOS振盪器。MEMS與FBAR的製程技術困難，無法與CMOS電路整合；而CMOS振盪器因半導體特性易受環境影響，導致其振盪頻率會因工作溫度與供應電壓的變動而改變。也因此，到目前為止石英振盪器還無法完全被取代。
因此我們致力於在CMOS電路設計上加上適當的補償方式將穩定度提高，使電路能在抵禦大幅度的溫度變化而幾乎不受影響。與一般弛張式震盪電路不同，本論文僅使用單一充放電迴路，可以有效降低頻率抖動(Jitter);並且加入除頻器，使得輸出訊號為一個責任週期(Duty Cycle)約為50%的方波。此晶片使用 TSMC 0.18 μm 1P6M標準製程實現。

Electronic platforms including communications, instruments and smart phones need clock generation to work properly. It means that the clock signal plays an important role in nearly all consumer electronic products. Therefore, how to generate an accurate and stable clock signal becomes one of the most important issues.
Recently, on-chip reference oscillators are required for low-cost single-chip applications including biomedical sensors, microcomputers, high-speed interfaces and SoCs. But most devices still require crystal oscillators (XO) serving as the frequency reference. Crystal oscillators possess some disadvantages such as high power consumption, being unable to be integrated into microelectronic process technology, and costing large area. For these reasons, researchers had been developing technologies in order to replace crystal oscillators.
These years, several methods such as MEMS, FBAR and CMOS oscillators have been proposed to solve above mentioned problems. Unfortunately, MEMS and FBAR oscillators need complex and costly processes to realize and they still cannot be integrated with CMOS circuits, and CMOS oscillator is sensitive to temperature and supply voltage variations. They are the reasons why crystal oscillators still cannot be replaced. Thus, we tried to develop a CMOS oscillator with high temperature stability.
In this paper, a CMOS relaxation oscillator which is nearly insensitive to temperature variation is proposed. Besides, by using single charging and discharging path and a frequency divider, low jitter and nearly 50% duty cycle were achieved. This chip has been realized in the TSMC 0.18 μm 1P6M process.

摘要 i
Abstract…….. ii
致謝……… iii
目 錄 iv
圖 目 錄 vii
表 目 錄 x
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文章節架構 6
第二章 研究理論 7
2.1 CMOS震盪器簡介 7
2.1.1 馳張式震盪(Relaxation Oscillator) 7
2.1.2 諧波震盪(Harmonic Oscillator) 8
2.2 頻率變異來源 10
2.2.1 製程變異(Process Variation) 10
2.2.2 供應電壓(Supply Voltage) 11
2.2.3 溫度(Temperature) 12
第三章 文獻回顧 14
3.1 平均電壓值回授(Voltage Average Feedback) 14
3.2 不受溫度影響之電阻 17
3.3 具溫度補償之弛張式震盪電路 22

第四章 電路架構 23
4.1 電路架構概述 23
4.2 子電路 24
4.2.1 Voltage Averaging Feedback 24
4.2.2 Operational Amplifier of VAF 26
4.2.3 比較器 28
4.2.4 固定轉導偏壓電路(Constant-Gm Biasing) 29
4.2.5 充放電路徑(RC Path) 32
4.2.6 Delay Buffer 34
4.2.7 除頻器 36
4.2.8 Control Buffer 37
4.2.9 Buffer Chain 38
4.3 震盪頻率 39
第五章 模擬與佈局 40
5.1 子電路模擬結果 40
5.1.1 Feedback OP Amplifier 40
5.1.2 比較器 42
5.1.3 偏壓電路 44
5.1.4 充放電路徑(RC Path) 47
5.1.5 Delay Buffer 50
5.1.6 除頻器 51
5.1.7 Control Buffer 52
5.2 整體電路模擬結果 53
5.2.1 震盪器波形 53
5.2.2 穩定時間(settling Time) 55
5.2.3 頻率受溫度之影響 56
5.2.4 頻率受供應電壓之影響 57
5.3 晶片布局 58
第六章 量測結果 61
6.1 PCB板的設計與環境架設 61
6.2 量測儀器介紹 62
6.3 量測方法 64
6.4 量測結果 66
6.4.1 震盪器輸出波形 66
6.4.2 頻率受供應電壓之影響 68
6.4.3 頻率受溫度之影響 69
6.4.4 週期抖動(Jitter)受溫度之影響 71
6.4.5 量測結果彙整 72
6.5 問題討論 74
第七章 結論與未來研究方向 77
7.1 結論 77
7.2 後續研究建議 77
參考資料 78
附錄 各製程邊界下之模擬結果 81

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