可攜帶的個人化電子裝置及物聯網( Internet of Things )的興起造成了對資料存取需求的增加。嵌入式非揮發記憶體(Embedded Nonvolatile Memory)能夠相容於CMOS邏輯製程，能與積體電路整合在同一晶片上，因此越來越受到重視。其中一次性寫入記憶體具有體積小，穩定性高的特點，通常被用作程式碼儲存，參數設定、電路校調即備援系統等方面的儲存。
本論文題出了相容於鰭式電晶體邏輯製程的N型一次寫入性記憶體，並且不需要額外的光罩或製程步驟。透過共用選擇電晶體的方式縮小每個位元所需要的面積，提高陣列的密度。此記憶體透過電晶體閘極介電層崩潰得現象作為寫入機制，能夠在低電壓的條件下進行寫入，寫入後有很高的讀取電流比。
本論文中提出的N型一次性寫入記憶體具有有低功耗、高可靠度、元件面積小等優點，且在製程方面無須多餘光罩並且可完全相容於16奈米高介電係數金屬閘極(high-κ metal gate, HKMG) CMOS之邏輯製程及具有高度微縮性，成為未來極具潛力的一次性寫入記憶體。

The rise of portable personal electronic devices and the Internet of Things has led to an increase in demand for data storage. Embedded Nonvolatile Memory can be compatible with CMOS logic process and can be integrated with microprocessor units on the same chip, so it has become in high demand. Due to its small volume and high stability, one time programmable memory (OTP) is usually used as the code storage, parameter settings, circuit trimming and memory redundancy, circuitry.
One-time programmable memory cell has been propose in this paper, besides, this memory cell is fully compatible with FinFET CMOS logic process, without any change in process flow and do not require additional mask. Cell density of this OTP is improved by a DINOR array. The OTP utilizes gate dielectric breakdown as the programming mechanism. Operated at a fairly low voltage, high On/Off read window can be also obtained for this cell.
With low power consumption, high reliability, compact cell size and scalability with FinFET high-κ metal gate CMOS process, this OTP shows great potential for future logic NVM applications

摘要 i
Abstract ii
內文目錄 iii
附圖目錄 v
附表目錄 vii
第一章 序論 1
1.1 一次性寫入記憶體簡介 2
1.2 一次性寫入記憶體結構與原理 2
1.3 一次性寫入記憶體分析及應用 3
1.4 一次性寫入記憶體最佳化設計 3
1.5 論文大綱 4
第二章 一次性寫入記憶體技術與發展 6
2.1 介電層電性崩潰式元件 6
2.1.1 XPMTM 6
2.1.2 1T-FuseTM 7
2.1.3 NeoFuseTM 7
2.1.4 XPMTM、1T-FuseTM及NeoFuseTM比較與討論 8
2.2 導電層熔毀式元件 8
2.3 電荷儲存式元件 9
2.4 特性比較 10
2.5 小結 11
第三章 一次性寫入記憶體 陣列結構與操作原理 19
3.1 元件結構與製程介紹 19
3.2 介電層電性崩潰機制與理論模型 21
3.2.1 熱化學崩潰模型 ( Thermochemical Model ) 21
3.2.2 陽極電洞注入模型 ( Anode Hole Injection Model ) 21
3.2.3 滲透模型 ( Percolation Model ) 22
3.2.4 從屬載子注入模型 ( Generated Subordinate Carrier
Injection Model ) 22
3.3 初始讀取電流傳導機制 23
3.3.1 直接穿隧 (Direct Tunneling)電流模型 23
3.3.2 F-N穿隧 (Fowler-Nordheim Tunneling)電流模型 23
3.3.3 陷阱輔助穿隧 (Trap Assisted Tunneling)電流模型 24
3.4 崩潰後之電性表現 24
3.5 陣列結構及操作分析 25
3.6 小結 26
第四章 一次性寫入記憶體元件量測與分析 39
4.1 量測環境介紹 39
4.2 元件基本電性量測 39
4.2.1 直流掃描崩潰測試 40
4.2.2 操作電壓對寫入速度的影響 40
4.2.3 寫入前後讀取電流量測 40
4.3 n=2之一次性寫入記憶體陣列特性分析 41
4.3.1 單記憶元寫入與讀取測試 41
4.3.2 記憶體陣列結構電性量測結果與分析 41
4.3.3 操作電壓與介電層崩潰後電流特徵量測與分析 43
4.3.4 寫入電壓對寫入速度的影響 44
4.4 元件可靠度分析 45
4.5 小結 46
第五章 Cross-point 陣列結構與模擬結果 67
5.1 Cross-point陣列結構 67
5.2 Cross-point陣列模擬結果 68
5.3 小結 69
第六章 總結 74
參考文獻 75

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