本論文內容主要呈現了兩個利用CMOS製程實現的2.5 Gbps以及10 Gbps高靈敏度光訊號接收器，高靈敏度的設計是由一個並聯回授的轉阻放大器(SF TIA)和一個頻率均衡器(CTLE)所組成。根據理論推導，加大回授電阻的阻值可以有效抑制輸入雜訊電流，同時產生更高的轉阻增益，但高增益會使的頻寬下降，因此我們使用一個頻率均衡器補償損失的頻寬；另外，後級的主動式回授限流放大器(Active feedback limiting amplifier)也可以提供高頻下的增益峰值，更進一步擴展了總體頻寬。
我們計劃進行三次的晶片下線，逐步驗證所前述的高靈敏度設計，雖然大多數設計都採用90奈米CMOS製程，我們也嘗試在先進製程（28nm）中設計更高數據速率（25Gbps）的光訊號接收器。
第一次下線主要用於驗證SF TIA + CTLE所提供的低雜訊特性，我們目標達成2.5 Gbps的數據速率開始，訊號非常低頻，如果遇到一些問題，可能更容易解決進行修正。第二次下線主要用於驗證主動式回授限流放大器的寬頻特性，我們在90 nm CMOS製程中目標實現10Gbps的傳輸速率；在28 nm CMOS製程中目標實現25Gbps的傳輸速率，這在當今的乙太骨幹網路中得到了廣泛的應用。由於前兩次下線沒有偏移消除回路來鎖定輸出DC共模準位，因此信號可能會出現不匹配問題。因此，我們多設計了偏移消除回路，並於第三次下線驗證DC偏移消除特性。
當晶片製造完成時，我們首先量測電性功能是否正常運作，一旦晶片正常工作，我們便將InGaAs PIN商用的檢光二極體打線與光接授器晶片做整合，便可量測光訊號靈敏度。量測結果顯示，在輸入訊號為PRBS9以及位元錯誤率(BER)10-12之下，我們所提出架構的2.5 Gbps光接受器靈敏度可達到-17 dBm，10 Gbps光接受器靈敏度可達到-10.6 dBm。除了與商用三五族檢光器做連接以外，我們還將光接收器晶片連接到矽光子IC的SiGe檢光二極體，並且量測到輸入信號僅需10.7μApp，亦可達到7.5Gbps的傳輸速率，此量測結果證明了我們所提出的低雜訊設計可以達到非常高的靈敏度。我們的設計不包含任何的電感，核心電路佔用的面積僅為0.121 mm2（2.5 Gbps光接收器）和0.145 mm2（10 Gbps光接收器）。 2.5 Gbps和10 Gbps光接收器的總功耗分別為72 mW和84 mW，由此可知，我們的設計不僅僅能在相同的傳輸速率下提供高靈敏度的性能，其功耗也低於大多數使用BJT做成的光接收器。

An inductorless 2.5 Gbps and an inductorless 10 Gbps high sensitivity CMOS optical receivers (Rx) are presented in this thesis. The high sensitivity design includes a shunt feedback (SF) trans-impedance amplifier (TIA) followed by an continuous-time linear equalizer (CTLE). A large shunt feedback resistor of the TIA could suppress the input-referred noise current, which results in a higher trans-impedance gain, but it trades off the bandwidth. An analog equalizer is therefore inserted to compensate the high frequency gain. The active feedback limiting amplifier (LA) provides gain peaking at high frequency that further extends the bandwidth.
We plan to tape out 3 times to verify the proposed high sensitivity design step by step. Although most of the design are implemented in 90 nm CMOS, we also attempt to design a higher data rate (25Gbps) optical Rx in the advance node (28nm).
The 1st tape-out is to verify the low noise performance of the SF TIA+CTLE design. We start from the data rate of 2.5 Gbps, which is a low data rate that could be easier for trouble shooting if we encounter some problems. The 2nd tape-out is to verify the broadband characteristic of the active feedback LA design. Our target is to realize low-noise CMOS optical receiver at the data rate of 10/25Gbps, which is widely used in the nowadays Ethernet backbone network. Since there is no offset cancellation loop to lock on the output DC common mode level in the past design, the signal may suffer from mismatch issues. We add a DC offset cancellation loop to solve this issue. Thus the 3rd tape-out is to verify the DC offset cancellation characteristic.
When chip is fabricated, we firstly characterize the electrical function is normal or not. Once the chip is working normally, an InGaAs PIN commercial photodiode is wire-bonded to the receiver chip to convert the optical signal to electrical signal. The measured results demonstrate a sensitivity of -17 dBm for a 2.5 Gbps optical Rx and -10.6 dBm for a 10 Gbps optical Rx at a BER of 10-12 with a PRBS9 input pattern. Aside from the commercial photodiode, we connect the receiver chip to a silicon photonic IC’s SiGe photodiode as well, proving the receiver’s high sensitivity performance would work normally with input current of only 10.7 μApp at the data rate of 7.5 Gbps. Without any inductor, the core circuit occupies an area of 0.121 mm2 for a 2.5 Gbps optical receiver and 0.145 mm2 for a 10 Gbps optical receiver. The total power consumption is 72 mW and 84 mW for 2.5 Gbps and 10 Gbps optical receiver, respectively. The measured power consumption is lower than most of the optical receivers in BJT under similar data rate and sensitivity performance.

Acknowledgments II
摘要 I
Abstract III
Content V
Figures IX
Tables XVI
Chapter 1. Introduction 1
1.1 Optical fiber communication systems 1
1.1.1 Basic concept 1
1.1.2 Protocols 4
1.2 Signal modulations 7
1.2.1 System level 7
1.2.2 ON-OFF keying, OOK 11
1.2.3 Pseudo-Random Binary Sequence, PRBS 16
1.2.4 Noise analysis 22
1.3 Optical devices 30
1.3.1 Laser diode 30
1.3.2 Mach zehnder modulator, MZM 32
1.3.3 Photo-diode, PD 33
1.3.4 Silicon Photonics 35
Chapter 2. Overview of Optical Receiver 36
2.1 Reference design 36
2.1.1 General specifications 36
2.1.2 State of the arts 38
2.1.3 Why CMOS? 40
2.1.4 Why inductorless? 43
2.2 PCB design 44
2.2.1 Why the PCB is needed for testing? 44
2.2.2 DC path consideration 45
2.2.3 Bond wire analysis and simulation 48
2.3 Measurement set-ups 51
2.3.1 Testing flow 51
2.3.2 Electric signal measurement 52
2.3.3 Optical signal measurement 54
Chapter 3. High-Sensitivity CMOS Optical Receiver analysis and design 59
3.1 Building blocks of proposed design 59
3.2 Circuit specifications 61
3.3 Trans-impedance amplifier (TIA) 62
3.2.1 Conventional CMOS topology 62
3.2.2 Adopted topology 70
3.2.3 High-sensitivity design of SF TIA 77
3.4 Continuous-time linear equalizer (CTLE) 80
3.3.1 Frequency response of CTLE 81
3.3.2 High-sensitivity and broadband design of SF TIA+CTLE 83
3.5 Limiting amplifier (LA) 85
3.4.1 Conventional LA 86
3.4.2 Active feedback LA 88
3.4.3 AM/PM conversion (jitter) 94
3.6 DC offset cancellation 97
3.5.1 DC offset issue 98
3.5.2 Design of DC offset cancellation loop 101
Chapter 4. High-Sensitivity CMOS Optical Receiver implementation and characterization 102
4.1 Tape-out sequence 102
4.2 2.5 Gbps optical receiver implemented in 90 nm CMOS. 103
4.2.1 Frequency response simulated results 104
4.2.2 Input-referred noise simulated results 106
4.2.3 Time-domain transient response simulated results 107
4.2.4 Layout and as-fabricated chip photo 107
4.2.5 Electrical signal measurement results 108
4.2.6 Optical signal measurement results 111
4.2.7 Case study-Si photonics IC + CMOS optical Rx measured results 112
4.3 10/25 Gbps optical receiver implemented in 90/28 nm CMOS 114
4.3.1 Frequency response simulated results 115
4.3.2 Input-referred noise simulated results 117
4.3.3 Time-domain transient response simulated results 118
4.3.4 Layout and as-fabricated chip photo 119
4.3.5 Electrical signal measurement results 120
4.3.6 Optical signal measurement results 123
4.3.7 Case study-Failed 25 Gbps optical Rx 125
4.4 Commercial product comparable 10 Gbps CMOS optical receiver 127
4.4.1 Reference design 128
4.4.2 Time-domain transient response simulated results 129
4.4.3 Layout and as-fabricated chip photo 130
4.4.4 Measured results 130
4.5 Comparison. 132
4.5.1 Comparison of simulated and measured results. 132
4.5.2 Comparison of electrical and optical measured results. 135
4.5.3 Compare the result of Si photonic IC’s SiGe PD with Ⅲ-Ⅴ PD. 136
4.5.4 Compare with other references. 137
4.5.5 Compare with commercial products. 138
Chapter 5. Conclusion & Future works 140
5.1 Conclusion 140
5.2 Future works-mmWave RoF ASIC 141
5.3 Reference 142

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