在現今科技生活中，可攜帶式電子產品已經是不可或缺的物品，而記憶體在這
些電子產品中更是扮演很重要的角色。隨著現今科技的進步，現今電子產品發展
更傾向輕薄短小且節能，因此許多研究單位大量投入次世代非揮發式記憶體的研
究。其中又以電阻式記憶體具有結構簡單、高密度、操作電壓低、讀寫速度快、
儲存時間長等優點，故被稱為最具有潛力的次世代非揮發式記憶體。
在本研究的第一部分，利用共濺鍍法將二氧化矽及金銀合金薄膜沈積利用黃光
微影製程定義的TiN 下電極之上，金銀合金成分分別為Au70Ag30 以及Au30Ag70
的CBRAM 元件進行電性量測分析。由於產生加凡尼反應的兩個必要條件，分別
是兩種不同活性金屬是否相接觸以及環境中是否存在電解質與兩金屬接觸。所以
本研究利用低溫電性量測平台在正常大氣環境、真空環境及水氣環境下對不同成
分的上電極所製作的CBRAM 元件進行電性量測。在實驗的過程中，發現只有在
金銀合金作為上電極且須在有水氣存在的情況時，Forming voltage 才會有明顯下降的趨勢，但若上電極是純銀電極的話則不管環境中是否有電解質存在，其
Forming voltage 都不會有明顯的變化趨勢，證實金銀合金作為上電極所發生現象極有可能是加凡尼反應(Galvanic effect)所造成。
在本研究的第二部分，由於前一部分研究發現電解質對於CBRAM 在電致成
型的過程扮演十分重要的角色，所以我設計了兩種不同的CBRAM 元件結構，我
們一樣利用濺鍍法來完成CBRAM 結構的製程，將二氧化矽、銅與碲化銅薄膜沉
積在黃光微影製程定義的TiN 下電極之上，其中一種元件結構是上電極為純銅，
中間層為二氧化矽，下電極為TiN;另一種元件結構與第一種結構類似，只是中間
層除了二氧化矽之外，再加上一層薄的固態電解質碲化銅(CuTe)，將兩種元件去
做電性分析量測之後，發現到有固態電解質的CBRAM 元件可以有較佳的特性，
如:較低的Forming Voltage，較小的操作電流與較大的記憶窗口等，造成這種現
象主要是因為Te 的存在會限制導通路徑銅阻絲的粗細，造成具有固態電解質的
CBRAM 元件的銅阻絲較細，故在阻態切換時，所需要的電荷數目較少，因此切
換速度較快。
在本研究的第三部分，由於前面的研究已經了解到電解質對於CBRAM 電性
上的影響，所以我們更進一步將CBRAM 元件結構改成中間層為固態電解質，研
究所使用的結構是上電極為銅，中間層為碲化銅，下電極為TiN 的CBRAM 元
件，實驗結果發現，中間層改成固態電解質碲化銅後，Forming Voltage 可以下降至1 V 左右，由於用來操作CBRAM 的MOSFET 的閘極氧化層已經微縮到了一
個物理極限，因此CBRAM 的Forming Voltage 勢必要下降，故本實驗此種元件
設計結構，提供了一個極佳的方法來解決微縮所面對的問題。
關鍵字: 電阻式記憶體，金銀合金電極，加凡尼反應，固態電解質

In today's technology life, portable electronic products are indispensable things, and memory plays an important role in these electronic products. With the advance of science and technology, electronic products tend to be thin, light and energy-saving
now; therefore, many research institutes devoted themselves to next generation nonvolatile memory research. RRAM has simple structure, high densities, low operating voltage, fast erase and write speed advantages among other non-volatile memory, so
RRAM is known as the most promising next generation non-volatile memory.
In this thesis first part, we used co-sputtering to deposit SiO2 and Au-Ag alloy thin film on photolithography defined TiN bottom electrode. The ingredient of Au-Ag alloy
is Au70Ag30 and the other is Au30Ag70, and these ingredient concentration CBRAM devices are used to do electrical measurement. Thanks to the two necessary conditions to occur Galvanic effect are two dissimilar conducting materials in electrical contact
with each other and exposed to an electrolyte; hence, we use electrical measurement station to measure the electrical property of different composition top electrode CBRAM devices in atmosphere, vacuum and vapor circumstances. During the execution of experiment, we found that only when Au-Ag alloy electrode
CBRAM devices exist in vapor ambient, the Forming Voltage tends to decrease.
In contrast, when top electrode is pure Ag, regardless of the presence of electrolyte in the circumstance, Forming Voltage will not have obvious decreasing tendency. These experimental results verify that the phenomenon are caused by Galvanic effect.
In this thesis second part, as we find that electrolyte plays an important role in the Forming process of CBRAM in the first part of thesis, so we design two different structure of CBRAM devices. We equally use sputtering to deposit SiO2, Cu, CuTe thin
film on photolithography defined TiN bottom electrode. The structure of the former device is Cu/SiO2/TiN, and the structure of the latter device is Cu/CuTe/SiO2/TiN, which is similar to the former device. The difference between two devices is that the
latter device has a thin solid electrolyte (CuTe) layer more. After doing electrical measurement of two devices, we found that the CBRAM device with solid electrolyte has better performance, for example: lower Forming Voltage, lower operating current
and larger memory window. These experimental results are caused by existence of Te.
Existence of Te will limit the size of Cu filament; hence, the CBRAM devices with solid electrolyte (CuTe) will have smaller size of filament. In conclusion, when CBRAM devices change resistive states, CBRAM devices with solid electrolyte need less charges, which causes faster switching speed.
In this thesis third part, we found that the effect of electrolyte on CBRAM before, so we manufacture a CBRAM device which structure is Cu/CuTe/TiN.
From the experimental results, Forming Voltage can be nearly 1 V. Thanks to that the gate oxide of MOSFET which is used to operate CBRAM is scaled down to physical limit; therefore, the Forming Voltage of CBRAM device must decrease. This structure of
CBRAM device can offer a good method to solve the problem of scaled down.
Key words: RRAM, Au-Ag alloy, Galvanic effect, Solid electrolyte

目錄
致謝.................................................................................................................................i
摘要................................................................................................................................ii
Abstract .........................................................................................................................iv
圖目錄............................................................................................................................x
表目錄........................................................................................................................ xiii
第 1 章:緒論..................................................................................................................1
1-1 前言.................................................................................................................1
1-2 研究動機.........................................................................................................2
第 2 章:文獻回顧..........................................................................................................3
2-1 次世代記憶體發展及簡介............................................................................3
2-1-1 鐵電式隨機存取記憶體(FeRAM) ......................................................3
2-1-2 磁阻式記憶體(MRAM).......................................................................4
2-1-3 相變化記憶體(PCRAM) .....................................................................5
2-1-4 電阻式記憶體(RRAM) .......................................................................6
2-2 電阻式記憶體切換機制.................................................................................9
2-2-1 阻絲理論(Filament-type theory)..........................................................9
2-2-2 介面效應 (Interface-type theory)......................................................10
2-3 電阻式記憶體的種類[11]............................................................................. 11
2-3-1 陰離子型RRAM (Anion Type RRAM)............................................ 11
2-3-2 陽離子型RRAM (Cation Type RRAM) ........................................... 11
2-3-3 Carbon-based RRAM......................................................................... 11
2-3-4 Oxide-based electrode RRAM ...........................................................12
2-4.絕緣體載子傳導機制...................................................................................13
2-4-1 歐姆傳導(Ohmic conduction)...........................................................13
2-4-2 蕭基發射(Schottky emission)...........................................................14
2-4-3 普爾-法蘭克發射(Poole-Frenkel emission) .............................................16
2-4-4 躍遷傳導機制(Hopping conduction) ...............................................17
2-4-5 穿隧效應 (Tunneling) ......................................................................18
2-4-6 空間電荷限制電流(Space charge limited current) ..........................19
第 3 章:實驗儀器設備與原理....................................................................................22
3-1 製程設備.......................................................................................................22
3-1-1 多靶磁控濺鍍系統 (Multi-Target Sputter) .....................................22
3-2 材料分析設備...............................................................................................23
3-2-1 傅立葉轉換紅外光譜儀 (Fourier-Transform Infrared Spectrometer)
......................................................................................................................23
3-2-2 X 光電子能譜 (XPS) ........................................................................26

3-2-3 N&K 薄膜特性分析儀 (N & K Analyzer) .......................................27
3-3 電性量測設備...............................................................................................28
3-3-1 半導體精準電性量測系統...............................................................28
第 4 章:金銀合金電橋式記憶體受環境氣氛影響之物理機制研究........................31
4-1 金銀合金電橋式記憶體製作流程..............................................................31
4-1-1 TiN 下電極基板之製備流程.............................................................31
4-1-2 中間層與金銀合金上電極之製備流程............................................32
4-2 材料分析.......................................................................................................33
4-2-1 中間層SiO2 的FTIR 分析...............................................................33
4-2-2 中間層SiO2 的N&K 分析................................................................34
4-2-3 金銀合金與SiO2 之XPS 分析........................................................34
4-3 金銀合金電極電橋式記憶體與純銀電極電橋式記憶體在氣氛環境變化時
對Forming Voltage 大小所造成的影響.............................................................37
4-3-1 Au30Ag70/SiO2/TiN CBRAM 元件在不同氣氛環境下之Forming
Voltage 大小比較.......................................................................................37
4-3-2 Au70Ag30/SiO2/TiN CBRAM 元件在不同氣氛環境下之Forming
Voltage 大小比較.......................................................................................39
4-3-3 Ag/SiO2/TiN CBRAM 元件在不同氣氛環境下之Forming Voltage
大小比較......................................................................................................41
4-3-4 加凡尼效應(Galvanic Effect)理論模型探討與分析.......................42
4-3-5 金銀合金電極厚度效應分析與探討...............................................46
4-3-6 模型建立與探討...............................................................................48
4-4 金銀合金上電極CBRAM 與純銀上電極CBRAM 之I-V 曲線與
Retention 可靠度分析.........................................................................................50
第 5 章:利用固態電解質碲化銅於電橋式記憶體所造成的影響之研究................54
5-1 電橋式記憶體元件製備流程......................................................................54
5-1-1 中間層與上電極的製備流程...........................................................54
5-1-2 中間層與上電極之濺鍍參數...........................................................55
5-2 加入固態電解質對電橋式記憶體所造成的影響......................................57
5-2-1 電橋式記憶體元件之Size Effect 電性量測...........................................57
5-2-2 電橋式記憶體元件之Forming Voltage 之量測與分析比較..........58
5-2-3 電橋式記憶體元件之I-V 曲線特性比較.......................................61
5-2-4 電橋式記憶體元件之切換時間比較...............................................64
5-2-5 電橋式記憶體元件之Sampling 數據結果比較..............................66
5-2-6 模型建立與分析探討.......................................................................69
第 6 章:利用固態電解質碲化銅作為中間層對於電橋式記憶體所造成的影響....70
6-1 電橋式記憶體元件製備流程......................................................................70
6-1-1 中間層與上電極的製備流程...........................................................70

6-1-2 中間層與上電極的濺鍍製備參數....................................................71
6-2-1 Cu/CuTe/TiN 電橋式記憶體元件之Size Effect 電性量測.............72
6-2-2 Cu/CuTe/TiN 電橋式記憶體元件之Forming Voltage 電性量測....73
6-2-3 Cu/CuTe/TiN 電橋式記憶體元件之I-V 曲線量測與分析.............74
6-2-4 Cu/CuTe/TiN 電橋式記憶體元件之切換時間量測與分析.............75
6-2-5 Cu/CuTe/TiN 電橋式記憶體元件之Sampling 數據結果比較........77
6-2-6 物理機制模型解釋與探討...............................................................80
6-2-7 理論模型驗證實驗結果與探討.......................................................81
6-3 三種CBRAM 元件之電性總比較..............................................................86
第 7 章:結論探討........................................................................................................89
第 8 章:未來研究方向................................................................................................91
Reference .....................................................................................................................92

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