近年來，諧振穿隧二極體 (Resonant-tunneling diode)、單電子電晶體 (Single-electron transistor)、量子點細胞運算器(Quantum cellular automata)等奈米元件的發展為臨界邏輯閘(Threshold logic gate)提供了可行的實作方式。也因此臨界邏輯閘相關的自動化研究一併蓬勃的發展起來。其中，臨界函數(Threshold function)的辨識在這些研究中算是最基礎但也最重要的。這是因為臨界邏輯電路(Threshold logic network)的合成、等價性驗證都需要一個快速的演算法來達成臨界函數的辨識。另一方面，邏輯合成在超大型積體電路設計流程中扮演著相當重要的角色。邏輯合成包含了多個優化的核心演算法，並進一步幫助我們提高電路的品質。因此，臨界邏輯電路的合成也是一個重要的研究方向。本篇論文針對這些問題提出了相對應的解決方法。

對於臨界函數辨識這個問題，我們提出了一個新的必要條件和對應的加速演算法。當被識別函數為單邊函數(unate function)但不是臨界函數時，過去的臨界函數辨識演算法可能會非常耗時。我們所提出的必要條件可以無縫地整合到既有的臨界函數辨識演算法中。與過去的方法相比，我們提出的必要條件可以加速臨界函數辨識。根據實驗結果，這個必要條件對於識別所有8個變數的臨界函數只會多花費0.1%的CPU時間。

除了我們提出的必要條件外，臨界函數的充分必要條件對於臨界函數辨識演算法也非常關鍵。實際上，幾十年前已經有學者提出了臨界函數的充分必要條件，這稱為求和定理(Summable theorem)。但是因為求和定理的高複雜度使得它無法實際應用在臨界函數辨識的問題中。因此，我們提出了新的定理來降低求和定理的複雜度。根據我們的實驗結果，對於一組6個變數到9個變數的單邊函數，我們所提出的加速理論平均可以節省76%到96%的計算量，以及40%到75%的CPU時間。

對於臨界邏輯電路的優化問題，我們觀察到並非所有的無關項(Don’t care)都能幫助減少臨界邏輯閘的成本。因此，在這個研究中，我們專注於計算能夠為減少臨界邏輯閘的成本的無關項。此外，我們採用了針對臨界邏輯閘的德摩根定律(De Morgan’s law)，從而實現同時考慮了成本和反相器(inverter)數量的臨界邏輯電路優化。根據實驗結果，對於一組臨界邏輯電路，我們所提出的方法跟之前的方法相比能夠有效地獲得更小的成本和更少的反相器。

Recently, many nanoscale devices had been developed, such as resonant tunneling diode, single-electron transistor, and quantum cellular automata, which provide promising and efficient implementations of Threshold Logic Gate (TLG). With the advances of implementing threshold logic devices, the design automation research on threshold logic has a rapid development. A fundamental but important topic in threshold logic is to determine whether a given function is a Threshold Function (TF) or not. This is because many applications, such as threshold logic synthesis and equivalence checking, need efficient and effective algorithms for TF identification. On the other hand, logic synthesis plays a crucial role in the VLSI design flow, and it contains optimization engines to improve the quality of design at the logic level. Therefore, as an alternative representation that is used to express a Boolean function, logic synthesis for Threshold Logic Networks (TLNs) is also an important research direction. Therefore, in this dissertation, we propose corresponding solutions to deal with these issues.

For the part of TF identification problem, the dissertation proposes a new necessary condition and the corresponding speedup strategies. The state-of-the-art to this identification problem could be very time-consuming when the function-under-identification is a non-TF with the unateness property. The proposed new necessary condition can be seamlessly integrated into this identification algorithm. As compared with the state-of-the-art, the improved identification algorithm with the proposed necessary condition can more effectively and efficiently detect non-TFs. Furthermore, according to the experimental results, the ratio of CPU time overhead in the process of checking the proposed necessary condition for identifying all the 8-input TF is only 0.1%.

In addition to the proposed necessary condition, knowing a sufficient and necessary condition for being a TF is quite crucial for TF identification algorithm. In fact, a sufficient and necessary condition for being a TF had been proposed many decades ago, which is called the Summable Theorem. However, this theorem and the corresponding checking algorithm are not practical from the viewpoint of efficiency due to the high complexity in implementation. As a result, in this dissertation, we propose several new theorems such that the complexity of the TF identification algorithm can be significantly reduced. Furthermore, according to the experimental results, 76%~96% computations are saved on average, and 40%~75% CPU time are saved on average, for a set of 6-input$\sim$9-input unate functions.

For the part of TLN optimization problem, we observed that not all the computed don’t cares contribute to the cost minimization of Threshold Logic Gate (TLG). Therefore, in this work, we focus on computing the don’t cares that effectively provide the opportunities for cost minimization. Furthermore, De Morgan's law for TLGs is applied such that global TLN optimization considering the cost and the number of inverters can be achieved. The experimental results show that the proposed approach is capable of obtaining a smaller cost and fewer inverters for a set of TLN benchmarks efficiently.

1. Introduction----------------------1
2. Preliminaries----------------------10
3. A New Necessary Condition for Threshold Function Identification----------------------17
4. On Reduction of Computations for Threshold Function Identification----------------------31
5. Don't Care Computation and De Morgan Transformation for Threshold Logic Network Optimization----------------------45
6. Conclusion and Future Work----------------------62

[1] T. Akeyoshi, K. Maezawa, and T. Mizutani, ``Weighted Sum Threshold Logic Operation of MOBILE Using Resonant-Tunneling Transistors,”IEEE Electron Device Letters, vol. 14, no. 10, pp. 475–477, 1993.


[2] M. J. Avedillo, J. M. Quintana, H. Pettenghi, P. M. Kelly, and C. J. Thompson, ``Multi-Threshold Threshold Logic Circuit Design using Resonant Tunnelling Devices,”Electronics Letters, vol. 39, pp. 1502-1504, 2003.

[3] I. A. Basheer and M. Hajmeerb, ``Artificial Neural Networks: Fundamentals, Computing, Design, and Application,”Journal of Microbiological Methods, pp. 3-31, 2000.

[4] V. Beiu, J. M. Quintana, and M. J. Avedillo, ``VLSI Implementations of Threshold Logic-a Comprehensive Survey,”IEEE Trans. on Neural Networks, pp. 1217-1243, 2003.

[5] P. Celinski, S. Cotofana, J. F. Lopez, and S. Al-Sarawi, ``State-of-the-Art in CMOS Threshold-Logic VLSI Gate Implementation,” in Proc. VLSI Circuits and Systems Conference, pp. 53-64, 2003.

[6] Y.-C. Chen, H.-J. Chang, L.-C. Zheng, ``Don’t-Care-Based Node Minimization for Threshold Logic Networks," in Proc. DAC, 2020.

[7] Y.-C. Chen, S. Eachempati, C.-Y. Wang, S. Datta, Y. Xie, and V. Narayanan, ``A Synthesis Algorithm for Reconfigurable Single Electron Transistor Arrays,” ACM Journal on Emerging Technologies in Computing System, Article 5, vol. 9, 2013.

[8] Y.-C. Chen, R. Wang, and Y.-P. Chang, ``Fast Synthesis of Threshold Logic Networks with Optimization," in Proc. ASPDAC, pp. 486-491, 2016.

[9] Y.-C. Chen, L.-C. Zheng, and F.-L. Wong, ``Optimization of Threshold Logic Networks with Node Merging and Wire Replacement," ACM Trans. on Design Automation of Electronic Systems, vol. 24, no. 6, article 67, 2019.

[10] Y. Crama, and P. L. Hammer, ``Boolean Functions: Theory, Algorithms, and Applications," Cambridge University Press, 2011.

[11] S. Eachempati, V. Saripalli, N. Vijaykrishnan, and Suman Datta, ``Reconfigurable Bdd-based Quantum Circuits,” in Proc. International Symposium on Nanoscale Architectures, pp. 61-67, 2008.

[12] D. Fan, M. Sharad, and K. Roy, ``Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic,”IEEE Trans. on Nanotechnology, Vol. 13, no. 3, pp. 574-583, 2014.

[13] L. Gao, F. Alibart, and D. B. Strukov, ``Programmable CMOS/Memristor Threshold Logic," IEEE Trans. on Nanotechnology, vol. 12, no. 2, pp. 115-119, 2013.

[14] H. Gao, Y. Yang, X. Ma, and G. Dong, ``Analysis of the Effect of LUT Size on FPGA Area and Delay using Theoretical Derivations," in Proc. International Symposium on Quality of Electronic Design, pp.370–374, 2005.

[15] M. J. Ghazala, ``Irredundant Disjunctive and Conjunctive forms of a Boolean function," I.B.M. Journal of Research and Development, vol. 1, pp. 171-176, 1957.

[16] T. Gowda, S. Vrudhula, and G. Konjevod, ``A Non-ILP Based Threshold Logic Synthesis Methodology,” in Proc. IWLS, pp. 222–229, 2007.

[17] D. Hampel and R. O. Winder, ``Threshold logic,”IEEE Spectrum, pp. 32-39, vol. 8, 1971.

[18] S. L. Hurst, ``Sequential Circuits using Threshold Logic Gates,”Int. Journal of Electronics, pp. 495-499, vol. 29, 1970.

[19] P.-Y. Kuo, C.-Y. Wang, and C.-Y. Huang, ``On Rewiring and Simplification for Canonicity in Threshold Logic Circuits," in Proc. ICCAD, pp. 396-403, 2011.

[20] C. Lageweg, S. Cotofana, and S. Vassiliadis, ``A Linear Threshold Gate Implementation in Single Electron Technology,” in Proc. IEEE Computer Society Workshop on VLSI, pp. 93-98, 2001.

[21] N.-Z. Lee and J.-H. R. Jiang, ``Constraint Solving for Synthesis and Verification of Threshold Logic Circuits," IEEE Trans. on Computer-Aided Design, Early access, 2020.

[22] N.-Z. Lee, H.-Y. Kuo, Y.-H. Lai, and J.-H. R. Jiang, ``Analytic Approaches to the Collapse Operation and Equivalence Verification of Threshold Logic Circuits," in Proc. ICCAD, pp. 30-37, 2016.

[23] S.-Y. Lee, N.-Z. Lee, and J.-H. R. Jiang, ``Canonicalization of Threshold Logic Representation and Its Applications," in Proc. ICCAD, pp. 1-8, 2018.

[24] C.-C. Lin, C.-H. Liu, Y.-C. Chen, C.-Y. Wang, and S. Yamashita, ``A New Necessary Condition for Threshold Function Identification," IEEE Trans. on Computer-Aided Design, vol. 39, No. 12, pp. 5304-5308, 2020.

[25] C.-C. Lin, C.-W. Huang, C.-Y. Wang and Y.-C. Chen, ``In\&Out: Restructuring for Threshold Logic Network Optimization," in Proc. ISQED, pp. 413-418, 2017.

[26] C.-C. Lin, C.-Y. Wang, Y.-C. Chen, and C.-Y. Huang, ``Rewiring for Threshold Logic Circuit Minimization," in Proc. DATE, pp. 1-6, 2014.

[27] C.-H. Liu, C.-C. Lin, Y.-C. Chen, C.-C. Wu, C.-Y. Wang, and S. Yamashita, ``Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments," IEEE Trans. on Computer-Aided Design, Vol. 38 , No. 12, pp. 2284 - 2297, 2019.

[28] S. Minato, ``Fast generation of prime-irredundant covers from binary decision diagrams," IEICE transactions on fundamentals of electronics, communications and computer sciences, vol. E76-A, no. 6, pp. 967- 973, 1993.

[29] A. Mishchenko, S. Chatterjee, and R. K. Brayton, ``DAG-aware AIG rewriting: A Fresh Look at Combinational Logic Synthesis," in Proc. DAC, 2006.

[30] S. Muroga,``Threshold Logic and Its Applications," New York, NY: John Wiley, 1971.

[31] S. F. Nafea and A. A. S. Dessouki, ``An accurate large-signal SPICE model for Resonant Tunneling Diode," in Proc. International Conference on Microelectronics, pp. 507-510, 2010.

[32] A. Neutzling, J. M. Matos, A. I. Reis, R. P. Ribas, and A. Mishchenko, ``Threshold Logic Synthesis Based on Cut Pruning," in Proc. ICCAD, pp. 494-499, 2015.

[33] A. Neutzling, J. M. Matos, A. Mishchenko, A. I. Reis, and R. P. Ribas, ``Effective Logic Synthesis for Threshold Logic Circuit Design," IEEE Trans. on Computer-Aided Design, vol. 38, no. 5, pp. 926-937, 2019.

[34] A. Neutzling, M. G. A. Martins, V. Callegaro, A. I. Reis, and R. P. Ribas, ``A Simple and Effective Heuristic Method for Threshold Logic Identification," IEEE Trans. on Computer-Aided Design, vol. 37, no. 5, pp. 1023-1036, 2018.

[35] A. K. Palaniswamy, M. K. Goparaju, and S. Tragoudas, ``An Efficient Heuristic to Identify Threshold Logic Functions,”ACM Journal on Emerging Technologies in Computing Systems, vol. 8, no. 3, pp. 1–17, 2012.

[36] M. Perkowski and A. Mishchenko, ``Logic Synthesis for Regular Fabric Realized in Quantum dot Cellular Automata,” Journal of Multiple-Valued Logic and Soft Computing, pp. 768-773, 2004.

[37] S. R. Petrick, ``Direct Determination of the Irredundant Forms of a Boolean Function from a Set of Prime Implicants," A.F. Cambridge Res. Center, Bedford, Mass., Report AFCRC-TR-56-110, 1956.

[38] H. Pettenghi, M. J. Avedillo, and J. M. Quintana, ``Improved Nanopipelined RTD Adder Using Generalized Threshold Gates,” IEEE Trans. on nanotechnology, vol. 10, no. 1, pp.155–162, Jan. 2011.

[39] W. V. Quine, ``The Problem of Simplifying Truth Functions," Am. Math. Monthly, vol. 59, pp. 521-531, 1952.

[40] J. Rajendran, H. Manem, R. Karri, and G S. Rose, ``Memristor Based Programmable Threshold Logic Array," in Proc. Nanoarch, pp. 5-10, 2010.

[41] V. Saripalli, L. Liu, S. Datta, and N. Vijaykrishnan, ``Energy-delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits,” Journal of Low Power Electronics,vol. 6, pp. 415-428, 2010.

[42] M. H. Sulieman, and V. Beiu, ``Characterization of a 16-Bit Threshold Logic Single Electron Technology Adder,” in Proc. ISCAS, pp. 681–684, 2004.

[43] P. Venkataramani, S. Srivastava, and S. Bhanja, ``Sequential Circuit Design in Quantum-dot Cellular Automata,” in Proc. Conference on Nanotechnology, pp. 534-537, 2008.

[44] P. Wang, M. Y.~Niamat, S. R.~Vemuru, M.~Alam, and T.~Killian, ``A Synthesis of Majority/Minority Logic Networks," IEEE Trans. on Nanotechnology, vol. 14, no. 3, pp. 473-483, 2015.

[45] R. O. Winder, ``Single Stage Threshold Logic,” Switching Circuit Theory and Logical Design, pp. 321-332, 1961.

[46] R. O. Winder, ``Threshold Logic,”Ph.D. dissertation, Princeton University, Princeton, NJ, 1962.

[47] R. O. Winder, ``Enumeration of Seven-Argument Threshold Functions,” IEEE Trans. on Electronic Computers, pp. 315-325, 1965.

[48] R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, ``Threshold Network Synthesis and Optimization and Its Application to Nanotechnologies," IEEE Trans. Computer-Aided Design, vol. 24, no. 1, pp.107-118, 2005.

[49] Y. Zheng, M. S. Hsiao, and C. Huang, ``SAT-based Equivalence Checking of Threshold Logic Designs for Nanotechnologies," in Proc. Great Lake Symp. VLSI, pp. 225-230, 2008.

[50] Y.-C. Chen, H.-J. Chang, and L.-C. Zheng. [Online]. Available: http://doi.org/10.5281/zenodo.3525945

[51] http://minisat.se/

[52] Berkeley logic synthesis and verification group. (2007) Abc: A system for sequential synthesis and verification, release 70930. [Online]. Available: http://www.eecs.berkeley.edu/~alanmi/abc/