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作者(中文):林毓傑
作者(外文):Lin, Yu-Chieh
論文名稱(中文):針對數位電路方塊的一個改良型混合高度標準元件擺置流程
論文名稱(外文):An Improved Mixed-Height Standard Cell Placement Flow for Digital Circuit Blocks
指導教授(中文):王廷基
指導教授(外文):Wang, Ting-Chi
口試委員(中文):陳宏明
麥偉基
口試委員(外文):Chen, Hung-Ming
Mak, Wai-Kei
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系所
學號:105062610
出版年(民國):107
畢業學年度:107
語文別:英文
論文頁數:27
中文關鍵詞:電子設計自動化混合高度標準元件元件擺放
外文關鍵詞:EDAMixed-Height Standard CellPlacement
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現今的晶片由多個不同的電路方塊所組成,而傳統上每個電路方塊是由同個標準元件庫所構成,標準元件庫通常會被設計成多種不同元件高度供選擇(例如在28奈米製程中有9軌和12軌高度的標準元件庫),每個標準元件庫皆由相同高度的元件所組成,高度較高的標準元件相較於高度較低的標準元件提供較好的效能但相對地會有較大的面積和功耗,因此一個聰明的設計策略乃是混合使用不同高度的標準元件庫來達到更好的設計品質。根據參考文獻中的[1],我們提出了一個改良型的混合高度標準元件擺放流程,我們在初始擺放階段與初始區域決定階段使用相同流程但不同的群聚方法去改良[1],同時在區域限制擺放階段開發了新的方法。前景看好的實驗結果展示了我們的流程相較於[1]更加優越。
There are various digital circuit blocks in a modern IC, and each block is typically made of standard cells all from a single standard cell library. Standard cell libraries are usually designed with different cell-heights (e.g., 9-track and 12-track cell libraries in a 28nm node) while each library contains standard cells of the same height. A standard cell of larger height provides better performance but inversely has larger area and consumes more power than one with smaller height. As a result, a smart strategy for designing a digital circuit block should try to mix the usage of cells with different heights for achieving better design quality. Based on a previous work [1] in this thesis, we present an improved mixed-height standard cell placement flow for digital circuit blocks. We enhance the placement flow of [1] by using the same flow but different clustering method in initial placement stage and initial region determination stage, and developing a different method to generate a mixed-height standard cell placement in region-constrained placement stage. Promising experimental results are reported to demonstrate the superiority of our placement flow over [1].
1 Introduction 1
2 ProblemFormulationandOverviewofOurPlacementFlow 5
2.1 ProblemFormulation........................... 5
2.2 OverviewofOurPlacementFlow.................... 6
3 InitialPlacement 8
3.1 1st Round Placement........................... 8
3.2 TargetCellClustering.......................... 8
3.2.1 GraphConstruction....................... 9
3.2.2 MarkovClusterAlgorithm.................... 9
3.2.3 Pre-processing.......................... 10
3.3 PseudoNetAdditionand2nd Round Placement............ 12
4 InitialRegionDeterminationandRegionUpdate 14
4.1 InitialRegionDetermination....................... 14
4.1.1 TargetCellRe-Clustering.................... 14
4.1.2 RegionDetermination...................... 15
4.2 RegionUpdate.............................. 15
5 Region-ConstrainedPlacement 16
5.1 Region-ConstrainedSingleCell-HeightPlacement........... 17
5.2 Region-ConstrainedTargetCellRe-placement............. 18
6 ExperimentalResults 19
7 Conclusion 25
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[9] S. v.Dongen, GraphClusteringbyFlowSimulation. PhDthesis,UniversityofUtrecht,2000.
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[11] Synopsys DesignCompiler. http://www.synopsys.com.
[12] OpenCoresDesign. http://opencores.org/.
[13] CadenceInnovus. http://www.cadence.com.
 
 
 
 
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