在先進製程中，通常會設計出不同高度的標準元件庫(例如在28奈米製程中便有9軌、12軌高度的標準元件庫)，每個標準元件庫皆由相同高度的元件所組成。相較於高度較低的標準元件，高度較高的標準元件提供較好的效能，但相對的會有較大的面積與功耗。現今的晶片通常會包含各式各樣的數位電路方塊，而各個數位電路方塊基本上只能使用同一個標準元件庫中的元件來設計。因應效能的需求，晶片內不同的數位電路方塊可能會使用不同高度的標準元件庫來設計。例如,對速度要求較低的數位電路方塊,為了降低其面積和功耗,會傾向使用高度較低的標準元件庫來設計;反之對速度要求較高的數位電路方塊,則傾向使用高度較高的標準元件庫來設計。一個較佳的設計策略乃是混合使用不同高度的標準元件庫來達到更好的效能。然而現今的設計流程或商用工具僅能針對不同數位電路方塊各自使用不同高度的標準元件來進行設計。在本篇論文中，我們提出一個能在單一數位電路方塊內實現混和高度元件擺置的流程，據我們所知，現今知名商用擺置工具仍未支援此流程的自動化。此外，我們整合商用擺置工具至我們提出的流程裏,針對流程中目前在學界和業界還未發展或尚未成熟的部分開發對應的軟體工具。

In advanced technology nodes, standard cell libraries are usually designed with different cell-heights (e.g., 9-track and 12-track cell libraries in a 28nm node) while each library contains standard cells of the same height. A standard cell of larger height provides better performance but inversely has larger area and consumes more power than one with smaller height. A modern IC usually includes various digital circuit blocks, and each block is typically made of standard cells all from the same cell library. Depending on the performance requirements, different blocks could be implemented using standard cells of different heights. For example, standard cells from a library with smaller height are desirable for blocks of low-speed applications so as to benefit the area and power reduction, while those from another library with larger cell-height are used for blocks of high-speed applications. Such a design approach, however, may not work properly for a digital circuit block that contains both low-speed and high-speed circuits. Consequently, a smart strategy for designing a digital circuit block should try to mix the usage of cells with different heights for achieving better design quality. Existing methodologies and tool flow can only mix cells with different height at block level (i.e., each block contains cells of a particular cell-height library). In this thesis, we propose a mixed-height standard cell placement flow to implement digital circuit blocks with mixed cell-height. To our best knowledge, commercial tools currently do not support this type of flow in a fully automated manner. In our placement flow, we leverage a commercial placement tool, and develop key point tools for those currently not available or not mature from the academia or industry community.

1 Introduction 1
2 Problem Formulation & Overview of Our Proposed Placement Flow 6
2.1 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Overview of Our Proposed Placement Flow . . . . . . . . . . . . . . . 7
3 Details of Our Proposed Placement Flow 10
3.1 Initial Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.1 1st Round Placement . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.2 Clustering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.3 Pseudo Nets Addition and 2nd Round Placement Considering
Pseudo Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Initial Region Determination . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.1 Re-Clustering . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.2 Region Determination . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Region-Constrained Placement . . . . . . . . . . . . . . . . . . . . . . 17
3.3.1 Mixed Cell-Height Placement . . . . . . . . . . . . . . . . . . 17
3.3.2 Single Cell-Height Placement . . . . . . . . . . . . . . . . . . 18
3.3.3 Placement Result Update . . . . . . . . . . . . . . . . . . . . 18
3.4 Region Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Experimental Results 21
5 Conclusion 28

[1] P. Gupta, A. B. Kahng, S. Nakagawa, S. Shah, and P. Sharma, "Mixed cell-height implementation for improved design quality in advanced nodes," in Proc. ICCAD, pp. 854-860, 2015.
[2] Y.-W. Chang, Z.-W. Jiang, and T.-C. Chen, "Essential issues in analytical placement algorithms," in IPSJ Trans. on Systems LSI Design Methodology, vol. 2, p. 145-166, 2009.
[3] I. Markov, J. Hu, and M.-C. Kim, "Progress and challenges in vlsi placement research," in Proc. ICCAD, pp. 275-282, 2012.
[4] M. Wang, X. Yang, and M. Sarrafzadeh, "Dragon2000: standard cell placement tool for large industry circuits," in Proc. ICCAD, pp. 260-263, 2000.
[5] C. Sechen and A. Sangiovanni-Vincenttelli, "The timberwolf placement and routing package," in IEEE Jounral of Solid-State Circuits, vol. SC-20, pp. 510-522, 1985.
[6] A. E. Caldwell, A. B. Kahng, and I. L. Markov, "Optimal partitioners and end-case placers for standard-cell layout," in IEEE Trans. Computer-Aided Design, vol. 19, pp. 1304-1313, 2000.
[7] M. C. Yildiz and P. H. Madden, "Improved cut sequences for partitioning based placement," in Proc. DAC, pp. 776-779, 2001.
[8] P. Spindler and F. M. Johannes, "Fast and robust quadratic placement combined with an exact linear net model," in Proc. ICCAD, pp. 179-186, 2006.
[9] N. Viswanathan and C. C. N. Chu, "Fastplace: efficient analytical placement using cell shifting, iterative local renement,and a hybrid net model," in IEEE Trans. Computer-Aided
Design, vol. 24, pp. 722-733, 2005.
[10] T. Hamada, C. K. Cheng, and P. M. Chau, "Prime: A timing-driven placement tool using a piecewise linear resistive network approach," in Proc. DAC, pp. 531-536, 1993.
[11] T. Kong, "A novel net weighting algorithm for timing-driven placement," in Proc. ICCAD, pp. 172-176, 2002.
[12] B. M. Reiss and G. G. Ettelt, "Speed: Fast and efficient timing driven placement," in Proc. ISCAS, pp. 377-380, 1995.
[13] Z.-W. Jiang, B.-Y. Su, and Y.-W. Chang, "Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs," in Proc. DAC, pp. 167-172, 2008.
[14] A. Kahng and Q. Wang, "Implementation and extensibility of an analytic placer," in IEEE Trans. Computer-Aided Design, vol. 24, pp. 734-747, 2005.
[15] C. Li, M. Xie, C.-K. Koh, J. Cong, and P. Madden, "Routability-driven placement and white space allocation," in Proc. ICCAD, pp. 394-401, 2004.
[16] P. Spindler and F. Johannes, "Fast and accurate routing demand estimation for efficient routability-driven placement," in Proc. DATE, pp. 1226-1231, 2007.
[17] K. Tsota, C.-K. Koh, and V. Balakrishnan, "Guiding global placement with wire density," in Proc. ICCAD, pp. 212-217, 2008.
[18] X. Yang, B.-K. Choi, and M. Sarrafzadeh, "Routability-driven white space allocation for fixxed-die standard-cell placement," in Proc. ISPD, pp. 42{47, 2002.
[19] Y. Cheon, P.-H. Ho, A. Kahng, S. Reda, and Q. Wang, "Power-aware placement," in Proc. DAC, pp. 795-800, 2005.
[20] H. Wu, I.-M. Liu, M. D. F. Wong, and Y. Wang, "Post-placement voltage island generation under performance requirement," in Proc. ICCAD, pp. 309-316, 2005.
[21] H. Wu and M. D. F. Wong, "Improving voltage assignment by outlier detection and incremental placement," in Proc. DAC, pp. 459-464, 2007.
[22] H. Wu, M. D. F. Wong, and I.-M. Liu, "Timing-constrained and voltage-island-aware voltage assignment," in Proc. DAC, pp. 429-432, 2006.
[23] R. L. S. Ching, E. F. Y. Young, K. C. K. Leung, and C. Chu, "Post-placement voltage island generation," in Proc. ICCAD, pp. 641-646, 2006.
[24] L. Guo, Y. Cai, Q. Zhou, and X. Hong, "Logic and layout aware voltage island generation for low power design," in Proc. ASP-DAC, pp. 666-671, 2007.
[25] S.-H. Baek, H.-Y. Kim, Y.-K. Lee, D.-Y. Jin, S.-C. Park, and J.-D. Cho, "Ultra high density standard cell library using multi-height cell structure," in Proc. SPIE, vol. 7268, pp. 72680C-
1-72680C-8, 2008.
[26] J. Chen, Z. Zhu, W. Zhu, and Y.-W. Chang, "Toward optimal legalization for mixed-cell height circuit designs," in Proc. DAC, pp. 1-6, 2017.
[27] C.-H. Wang, Y.-Y. Wu, J. Chen, Y.-W. Chang, S.-Y. Kuo, W. Zhu, and G. Fan, "An effective legalization algorithm for mixed-cell-height standard cells," in Proc. ASP-DAC, pp. 450-455,
2017.
[28] C.-Y. Hung, P.-Y. Chou, and W.-K. Mak, "Mixed-cell-height standard cell placement legalization," in Proc. GLSVLSI, pp. 149-154, 2017.
[29] G. Wu and C. Chu, "Detailed placement algorithm for vlsi design with double-row height standard cells," in IEEE Trans. Computer-Aided Design, vol. 35, pp. 1569-1573, 2016.
[30] Y. Lin, B. Yu, X. Xu, J.-R. Gao, N. Viswanathan, W.-H. Liu, Z. Li, C. J. Alpert, and D. Z. Pan, "Mrdp: Multiple-row detailed placement of heterogeneoussized cells for advanced nodes,"
in Proc. ICCAD, pp. 1-8, 2016.
[31] Synopsys Design Compiler. http://www.synopsys.com.
[32] OpenCores Design. http://opencores.org/.
[33] Cadence Innovus. http://www.cadence.com.