近年來興起的邊緣運算期望將中央伺服器上的計算和⼈⼯智慧相關應⽤逐漸移動到靠近資料來源的終端設備上，以達成快速的執⾏回覆時間並減少終端設備到中央伺服器間的網路傳輸。在邊緣運算中，終端設備提供各式各樣的應⽤程式或服務如針對終端設備所蒐集到的數據做預處理，使⽤⼈⼯智慧做判斷或多媒體⼈機互動界⾯等。在這些應⽤程式中，有許多應⽤是⾮常適合使⽤特定⽤途的硬體加速器來加速其運算⼯作。隨著終端設備上加速器數量越來越多，由⼀個或多個微控制與主處理器所組成的⾮對稱異質多核⼼架構是⼀個極具淺⼒且被看好的
硬體架構。在此架構中，主處理器對加速器之排程和中斷處理⼯作將會由微處理器代為執⾏。詳細架構如NVIDIA 深度學習加速器（NVDLA）中所⽰。為了開發⾮對稱異質多核⼼架構的邊緣運算系統，經常在開發階段中使⽤如QEMU 的虛擬平台提前進⾏效能評估或功能驗證。可惜的是，QEMU 只有提供對稱同質多核⼼系統的模擬，並沒有模擬⾮對稱異質多核⼼系統。在本論⽂中，我們透過兩種可能的實現策略來解決在QEMU 上實現⾮對稱異質多核⼼系統的問題：單進程和多進程。最後，對於這兩種⽅法分別進⾏數據⽐較及討論。

he emerging edge computing is poised to move computing and intelligence to the network's edge so as to be close to the data sources for fast responses and reduced network traffic. In edge computing, edge devices need to encompass a wide variety of applications or services, from data preprocessing, intelligence inference, to multimedia human interface. Many such applications are well suited for special-purpose hardware accelerators. With the increasing number of accelerators on the edge devices, a promising architecture for edge devices is an asymmetric heterogeneous multicore that incorporates one or more microcontrollers to offload accelerator scheduling and interrupt handling from the main CPU, as exemplified in the NVIDIA Deep Learning Accelerator (NVDLA). To develop such computing systems, virtual platforms such as QEMU are often used. Unfortunately, QEMU only supports symmetric homogeneous multicore systems. In this paper, we tackle the challenging problem of supporting asymmetric heterogeneous multicore systems on QEMU by considering two possible implementation strategies: one-process and multi-process. The two strategies are implemented and compared qualitatively and quantitatively.

Abstract
Contents
List of Figures
List of Tables
1 Introduction 1
2 Background 6
2.1 QEMU . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.1 Overall architecture . . . . . . . . . . . . . . . 7
2.1.2 Dynamic binary translation . . . . . . . . . . . . 7
2.1.3 Full system emulation . . . . . . . . . . . . . . 8
2.1.4 User emulation . . . . . . . . . . . . . . . . . . 9
2.2 Library . . . . . . . . . . . . . . . . . . . . . . . 9
3 System Design 12
3.1 System architecture . . . . . . . . . . . . . . . . . 12
3.2 System flow . . . . . . . . . . . . . . . . . . . . . 15
4 Implementation 17
4.1 One-process methodology . . . . . . . . . . . . . . . 17
4.2 Multi-process methodology . . . . . . . . . . . . . . 22
5 Experiments 24
5.1 Validation . . . . . . . . . . . . . . . . . . . . . 25
5.2 Time distribution . . . . . . . . . . . . . . . . . . 25
5.3 Comparison of the two proposed methodologies . . . . 27
6 Conclusions 33

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