隨著科技的進步，人們對於資料傳輸量的需求也越來越大，所以我們希望傳輸速度可以一直無限上升，而並列輸出又會造成電磁干擾和串音等問題，亦會使電路板上的繞線更加複雜，因此串列器∕解串器在許多應用上都扮演著非常重要的角色。
在如此高頻率的操作下通道的衰減非常的大，也會產生嚴重的符號間干擾，使得傳輸出去的位元前後互相干擾而使眼圖上的眼狀振幅變小甚至消失，因此位元誤碼率會大幅上升。
而傳送端為了抑制電磁干擾，常會以展頻時脈來分散中心頻率的能量，高頻的諧波也會被分散開，因此可以降低對其他訊號的干擾。
為了解決上述通道的衰減問題，我們必須在接收端前面加上用來補償的等化器，使得衰減的訊號可以被還原回來，在眼圖上面呈現開眼的狀態，讓後面的時脈資料回復電路可以正確的判斷出原本的訊號，以產生正確的時脈把接收到的資料還原回來。
而等化器的部分必須隨著環境的不同而有自我調整的功能，因為不同長度的通道就會不同的衰減量，本論文的目在PCIE 3.0（5 inch）的通道下做出可適應性的等化器，以及對於傳送端經過展頻後傳送的資料，以時脈資料回復做還原，並且再把串列的資料用解串器還原成並列的資料。

With the advancement of technology, people are demanding the amount of data transmission. Therefore, we hope that the transmission speed can be increased significantly. And the parallel output will cause problems such as electromagnetic interference and crosstalk. It will also cause problems on the circuit boards. Windings are more complicated, so serializer plays a very important role in many applications.
With such high-frequency operation, the attenuation of the channel is very large, and serious inter-symbol interference may also occur, which causes the transmitted bits to interfere with each other and cause the eye amplitude on the eye diagram to become smaller or even disappear. Therefore, the bit error occurs dramatically.
In order to suppress the electromagnetic interference, the transmitter often uses spread spectrum clocking to disperse the energy of the center frequency, and the high-frequency harmonics are also dispersed, which can reduce the interference to other signals.
In order to solve the problem of attenuation of the channel above-mentioned, we must add an equalizer for compensation in front of the receiver, so that the attenuated signal can be reconstructed, and the open-eye state appears on the eye diagram, thus the clock and data recovery circuit works at the back. The original signal can be correctly judged to generate the correct clock to recover the received data.
The equalizer must has self-adjustment function according to the environment, because different lengths of channel will have different attenuations. The purpose of this thesis is to make equalizer adaptable while using the PCIE 3.0 (5 inch) channel. And recovery the data transmitted by spread spectrum clocking by the clock data recovery. Then the serial data is recover to the parallel data by the deserializer.

摘要 i
Abstract ii
致謝 iv
目錄 v
圖目錄 vii
表目錄 x
第一章 緒論 1
1.1研究動機 1
1.2論文介紹 3
第二章 高速串列傳輸 4
2.1通道特性 4
2.2資料傳輸方式 6
2.3頻寬限制 7
2.4訊號雜訊比與位元誤碼率 8
2.5傳送端 9
第三章 連續時間線性等化器 13
3.1等化器簡介 13
3.2高頻補償技術 14
3.3高頻增益控制之可適應性等化器 17
3.4逆向縮放比例 23
第四章 鎖相迴路 24
4.1鎖相迴路數學模型 24
4.2迴路穩定性及雜訊分析 26
4.3子電路及其非理想效應 29
第五章 時脈資料回復 39
5.1抖動的介紹 39
5.2時脈抖動的特性與規格 40
5.3子電路設計 44
第六章 模擬結果 50
參考文獻 54

[1] Chin-Yuan Wei, A Multi-band Fast Lock Clock and Data Recovery Circuit
[2] Wen-Chieh Huang, Clock and Data Recovery Circuit and Equalizer for High-Speed Serial-Link Receiver
[3] Shen-Kai You, A 6Gb/s 40dB Digitally Adaptive Equalizer for Burst-Mode Applications
[4] Che-Fu Liang, A Jitter-Tolerance-Enhance CDR Using a GDCO-Based Phase Detector
[5] Xiaojian Mao, New Frequency Divider with 8 Output Phases for Phase Switching Prescaler
[6] Shih-Lun Chen, An All-Digital Delay-Locked Loop for High-Speed Memory Interface Applications
[7] Wei-Tsuen Chen, A Delta-Sigma Phase Locked Loop with 2.8-4.8 GHz tuning range
[8] Jri Lee, Design of Communication ICs
[9] 劉深淵、楊清淵，鎖相迴路
[10] 高曜煌，射頻鎖相迴路IC設計