隨著人工智慧時代來臨，深度神經網絡（DNN）已經證明對各種應用有效，例如圖像處理，視頻分割和語音識別。在當前系統上運行現有的DNN主要依賴於通用處理器，ASIC設計或FPGA加速器，由於有限的片上存儲器和數據傳輸帶寬，所有這些都受到數據移動的影響。因此傳統馮‧紐曼計算機體系結構中的“存儲器牆”，處理器和存儲器之間的有限帶寬已成為提高系統性能的最關鍵瓶頸之一。記憶體內運算主要的設計組成概念包括：將資料存放在記憶體中以加快處理的速度、透過壓縮技術減少資料量、減少資料的移動，僅搬移運算後的結果，而非搬移資料去運算、利用內存計算，提高處理效率。
本篇論文提出了一個以非揮發性電阻式記憶體 (ReRAM)為基礎的記憶體內運算功能，在此架構可以接收輸入訊號與儲存權重的能力，讓一個周期內實現乘法與累加運算功能，意即可以減少資料在中央處裡單元(CPU) 與記憶體之間傳輸量以及傳輸過程中的能量損耗。論文中將探討揮發性記憶體內運算(nv-CIM)運算過後讀取上會面臨之挑戰，並提出兩個解決方案(1)輸入模式感知補償生成方案 (2)電壓感測放大器電路解決以下問題，以提升讀取效能:
1.在有限的R比率下，不同的輸入導致相同的乘法和累加值(MACV)的電流或電壓的顯著飄移變化，甚至相鄰的MACV重疊，導致讀取失敗。利用輸入模式感知補償生成方案，可以避免每個MAC value重疊現象發生。
2.在低阻值率下，感測放大器使用雙參考電壓取代傳統中點參考電壓，可以抑制產生參考電壓的製程變異後的分布，並且增強原本偏小的感測裕度。
透過55奈米邏輯製程，本篇論文實現了容量為0.5Mb之基於ReRAM的記憶體內具有運算功能的架構。與先前的論文相比，在記憶體內運算模式中，所提出來的架構降低了將近3X的能量損耗。而量測結果，在記憶體內運算模式下，量測讀取速度達到了9.7ns的，在ReRAM模式下，量測讀取速度達到2.5ns。我們提出的感測放大器，相較於傳統電壓感測放大器，可以容忍7.4倍之輸入飄移能力。

With the advent of artificial intelligence, Deep neural networks (DNN) have demonstrated effectiveness for various applications such as image processing, video segmentation, and speech recognition. Running state-of-theart DNNs on current systems mostly relies on either general purpose processors, ASIC designs, or FPGA accelerators, all of which suffer from data movements due to the limited onchip memory and data transfer bandwidth. Therefore, the “memory wall” in conventional Von-Neumann computer architectures, the limited bandwidth between processors and memories has become one of the most critical bottlenecks to improve system performance. The main design components of computing in memory include: storing data in memory to speed up processing, reducing data volume through compression technology, reducing data movement, and only moving the results after calculation, instead of moving data to calculate and utilize computing in memory for improved processing efficiency.
This paper proposes a computing in memory function based on non-volatile resistive memory (ReRAM), in which the architecture can receive input signals and store weights, enabling multiplication and accumulation operations in one cycle. This means that the amount of data transferred between the CPU and the memory and the energy loss in the process can be reduced. In this paper, we will discuss the challenges of reading in non-volatile computing in memory (nv-CIM) and propose two solutions. (1) Input-pattern aware compensate generation scheme (2) Voltage sense amplifier.
The circuits solve the following problems to improve read performance:
1. At a limited R ratio, different inputs result in significant shifts in current or voltage at the same MAC value, even overlapping adjacent MAC values, resulting in reading failure. The use of the input-pattern aware compensate generation scheme can avoid the occurrence of each MAC value overlap phenomenon.
2. At small R-ratio, the voltage sense amplifier replaces the traditional midpoint reference voltage with a dual reference voltage, which suppresses the process variations of reference voltage distribution and enhances the original small sense margin.
Through the 55nm logic process, this paper implements an architecture with computational capabilities in a 0.5Mb ReRAM-based memory. Compared with the previous papers, computing in-memory mode, this paper reduces the energy loss of nearly 3X. The measurement results, in the nv-CIM mode, this paper reached the measurement read speed of 9.7ns, in the ReRAM mode, it reached the measurement read speed of 2.5ns. Our proposed sense amplifier can tolerate 7.4 times the input offset capability compared to conventional voltage sense amplifiers.

摘要 i
Abstract iii
List of Tables x
Chapter 1 Introduction 1
1.1 The Role of Memory in SoC products 1
1.2 Memory Landscape 3
1.2.1 RAM 5
1.2.2 CAM 5
1.2.3 ROM 6
1.2.4 Programmable NVMs 6
1.3 Von Neumann bottleneck 7
1.4 Schematic of the Deep Neural Network (DNN) 9
1.5 Computing-In-Memory (CIM) 10
Chapter 2 Characteristic of Contact-ReRAM 11
2.1 Structure of Contact-ReRAM 11
2.2 Write Operation 13
2.3 Read Operation 15
2.4 Distribution of Contact-ReRAM 16
Chapter 3 17
3.1 Structure and Operations of nv-CIM Read 17
3.2 Design Challenges 18
3.3 Previous Arts 19
3.3.1 Input Aware Reference Based ReRAM　CIM 20
3.3.2 Neural-Network(NN) based on Resistive Analog Neuro Device 23
3.3.3 Summary 25
Chapter 4 25
4.1.1 Motivation and Concept of Proposed ReRAM based CIM 26
4.1.2 Input-pattern aware compensate generation scheme 27
4.1.3 Operation 28
4.2 Analysis and Comparison for nv-CIM Scheme 31
4.2.1 Analysis Sensing margin of scheme 31
4.2.2 WLs on quantity versus to power consumption and Devolving time 32
4.2.3 Speed Comparison for nv-CIM scheme 32
4.2.4 Power Comparison for nv-CIM scheme 33
4.2.5 Energy Comparison for nv-CIM scheme 34
4.2.1 Analysis Read Yield of Macro 35
4.3 Structure and operations of proposed read I/O 36
4.4 Analysis and Comparison for nv-CIM Macro 38
4.4.1 Speed Comparison for nv-CIM Macro 39
4.4.2 Energy Comparison for nv-CIM Macro 40
Chapter 5 42
5.1 Design Challenges of Small Sensing Margin 42
5.1.1 Threshold Voltage in Process 42
5.1.2 Issues of Small R-ratio Devices 43
5.2 Structure and Operation of Conventional Sensing Schemes 45
Chapter 6 Proposed SA Circuits Schemes and Analysis 48
6.1 Concept of Proposed Sense Amplifier 48
6.2 Structure of Proposed Sense Amplifier 53
6.3 Operations of Proposed Sense Amplifier 54
6.4 Analysis and Comparison for SA 60
6.4.1 Efficiency of Margin Enhancement 60
Chapter 7 Measurement Results and Conclusion 64
7.1 ReRAM Macro 64
7.2 Design for Testchip 67
7.3 Conclusions and Future Work 75
Reference 77

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