NAND 快閃記憶體 (NAND Flash Memory) 被廣泛應用於資料的儲存，做為固態硬碟 (SSD)、SD 卡和 eMMC 晶片底層的儲存媒體，然而由於快閃記憶體在儲存上的特性，當經過一段時間後儲存單元 (Flash Cell) 中的閾值電壓值會發生偏移，而導致資料錯誤，即為保存錯誤(Retention Error)，而在長時間的保存下，資料可能因保存錯誤而產生高錯誤率，而超過其錯誤更正碼能修正錯誤的能力範圍。本篇研究針對在長時間斷電下，因保存錯誤導致高錯誤率而無法單以錯誤更正碼修正的資料提出修復的機制，我們的實驗實際將資料寫入一 16 奈米的TLC(Triple-Level Cell) 快閃記憶體中，並使其中的資料歷經相當於 10年的保存時間，分析儲存單元因保存錯誤而發生的情況。針對 TLC 快閃記憶體在保存錯誤上的觀察，我們發現在不同的儲存單元狀態下 (Cell State) 其閾值電壓值偏移情形而有不同，依此特性設計了兩項修復機制，首先我們依不同的儲存單元狀態，皆以最佳的閾值電壓準位 (Threshold Voltage Boundary) 來讀取資料，其次我們於資料最初寫入時，記錄了與預設閾值電壓值接近的儲存單元，這些儲存單元在經過長時間保存下容易產生保存錯誤，透過事先的紀錄用於將來修正資料。我們藉由兩項機制來降低資料錯誤率，使錯誤更正碼得以修正資料，來達到資料的修復，本研究實驗結果最高可減少 62% 的保存錯誤，額外的儲存空間成本約為4.67%。

NAND flash memory is widely used for data storage in device stor-age medium, such as solid state drives (SSD), SD cards, and eMMC chips. Due to the characteristics of flash memory, when data stored in flash cell over time, the threshold voltage of flash cell will shift and cause retention error. Bit error rate (BER) increase with long-term storage. While higher BER exceeding the correction ability of error correction code (ECC), the data will corrupt with ECC decoding failure. For long-term power failure situation with flash memory, we propose a repair technique for data which with high error rates, that cannot be corrected by error correction codes alone. Our experiments write data into a 16 nm TLC (Triple-Level Cell) flash memory and the data has been stored for a period equivalent to 10 years retention time. According to analyzing these cell state errors caused by reten-tion, and we found the threshold voltage of different cell state shifts with unequal degree. Based on this characteristic, we design two re-pair techniques. First, for the different cell states, read with optimal threshold voltage boundary. Second, when the data was first written, we recorded the cells that were close to the default threshold voltage boundary. These cells tend to incur error with long-term retention time. By record these cells in advance, and used to correct retention errors. We use two techniques to reduce data error rate, so that the ECC can be decoded and the data achieve complete recovery. Experimental results show that the proposed techniques can reduce the retention error up to 62% and the additional storage overhead is about 4.67% compared to original data size.

誌謝. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Abstract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Background. . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 TLC NAND Flash Memory . . . . . . . . . . . . . . . . . . . . 4
2.1.1 NAND Flash Cell . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Cell State and Retention Error . . . . . . . . . . . . . . . . 5
2.3 Read Retry . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.1 Read Retry Flow . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Error Correction Code . . . . . . . . . . . . . . . . . . . . 7
3 Observation. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Optimal Threshold Voltage . . . . . . . . . . . . . . . . . . 9
3.2 Flash Cell 電壓值的偏移現象 . . . . . . . . . . . . . . . . . . 11
4 Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Merge Cell States with Optimal Vth boundary . . . . . . . . . 12
4.2 Record cells to correct retention error . . . . . . . . . . . 16
4.2.1 依 cell state 選擇適合的 Vth boundary 來讀取記錄 flash cell . . 17
4.2.2 記錄及更正資料方法 . . . . . . . . . . . . . . . . . . . . . . 18
4.2.3 記錄和更正流程圖 . . . . . . . . . . . . . . . . . . . . . . . 21
5 Evaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 實驗設置 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Cell State Optimal Vth Merge 效果評估 . . . . . . . . . . . . . 24
5.2.1 Overhead 和效益分析 . . . . . . . . . . . . . . . . . . . . . 25
5.3 Recorded Cells Correction 效果評估 . . . . . . . . . . . . . . . 26
5.3.1 Overhead 和效益分析 . . . . . . . . . . . . . . . . . . . . . 28
5.4 整體效果評估 . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.4.1 Storage Overhead . . . . . . . . . . . . . . . . . . . . . . 29
5.4.2 ECC Capability 評估 . . . . . . . . . . . . . . . . . . . . . 30
6 Related Work. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7 Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8 Future Work. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

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