隨著科技的演進，無線通訊的傳輸速率要求也隨之增加，行動通訊系統也從2G一路演進到目前最新的5G，並隨著近十年來智慧型手機爆發性的成長之賜，人們對於頻寬的需求與時俱進，串流音樂、影音也因為無線網路的發達而崛起，光以影音規格來說，很快地，人們就不會滿足於 Full HD 的解析度，而會想要往 4K、甚至 8K 的解析度邁進，人們對於無線網路的速度需求只會越來越大，因此一旦 5G 逐漸普及，許多需要更快下載速度的服務與應用也會迅速流行。
　　本論文提出一個應用在5G NR所定義的毫米波頻段射頻收發機的三百五十億赫茲具有三角積分調變器的數位式鎖相迴路，主要組成電路有參考信號預除器、相位頻率檢測器、電流幫浦、晶片內的迴路濾波器、可選頻帶之LC式壓控震盪器、電流模式除頻器、與具有三角積分調變器控制之除頻器，利用運算放大器降低電流幫浦的非理想效應，而在電流幫浦中設計可調整電流，藉此改變迴路頻寬，並在相位頻率檢測器中加入延遲電路，可在Reference Spur最小的情況下解決死區的問題，並用切換式電容層降低單一頻帶壓控振盪器的增益來提升相位雜訊的表現，而論文中三角積分調變器擁有十六位元達到所需除數的高解析度輸出。而因為此次應用，必須要有四組17GHz的I/Q正交訊號，以利用四種不同的相位差，由於晶片面積的考量，不同以往運用注入式鎖定除頻器，本論文將電流模式除頻器直接當作35GHz壓控振盪器的下一級，做後續降頻的動作，由以上子電路建立出完整的鎖相迴路架構。
本論文採用台積電所提供之六十五奈米CMOS製程進行模擬設計，論文開頭為介紹鎖相迴路架中個子電路的核心概念和操作原理，接著依序講解鎖相迴路設計流程、數學模型、提出電路架構之模擬結果、下線晶片的量測考量，最後對於提出之鎖相迴路做統合性的結論。

With the evolution of technology, the transmission rate requirements of wireless communication have also increased. The mobile communication system has also evolved from 2G to the latest 5G. With the explosive growth of smart phones in the past decade, people have been The wide demand keeps pace with the times. Streaming music and audio and video are also rising due to the development of wireless networks. In terms of audio and video specifications, people will not be satisfied with the resolution of Full HD and will want to As the resolution of 4K and even 8K, people's demand for wireless network speed will only increase. As soon as 5G becomes popular, many services and applications that require faster download speeds will quickly become popular.
A 35GHz Phase Locked Loop with Delta Sigma Modulator applied to a millimeter-wave band RF transceiver as defined by 5G NR was proposed in this thesis. The main components of the circuit are a reference pre-divider, phase-frequency detector, charge pump,3^rd loop filter on chip, LC voltage controlled oscillator of selectable frequency band, current mode logic frequency divider, and a divider controlled by delta-sigma modulator. Using operational amplifier to reduce the non-ideal effect of charge pump, while designing the adjustable current in the charge pump, to change the loop bandwidth, and adding a delay circuit to the phase frequency detector, can solve the dead zone with the minimum Reference Spur. I use the switching capacitive layer to reduce the gain of the single-band voltage-controlled oscillator to improve the performance of phase noise. In the thesis, the delta-sigma modulator has 16 bits to achieve the high resolution output of the required divisor. Because of the application, there must be four groups of 17GHz I/Q quadrature signals to utilize four different phase. Due to the consideration of the chip area, different uses of injection locking frequency dividers in the past. In the thesis, will use CML frequency divider to be the next stage of the 35GHz voltage controlled oscillator to reduce frequency successfully. The entire architecture of proposed PLL was composed by the circuits mentioned above.
The design of this thesis uses the 65 nanometer CMOS process was provided by TSMC.The thesis begins with the introduction of the core concepts and operating principles of a sub-circuit in a PLL. and the mathematical model of PLLs, the designed flow, the simulation results of proposed circuits, the considerations of measurement were described step by step. Finally, an integrated conclusion for the proposed PLL was given in the last chapter.

中文摘要 I
ABSTRACT II
目錄 IV
圖目錄 VI
表目錄 XI
1.1研究動機 1
1.2 論文大綱 2
第二章 鎖相迴路架構介紹與設計原理 3
2.1鎖相迴路基本介紹 3
2.2鎖相迴路子電路介紹 3
2.2.1相位頻率檢測器 3
2.2.2電流幫浦 7
2.2.3迴路濾波器 11
2.2.4電壓控制振盪器 17
2.2.5除頻器 28
2.3鎖相迴路轉移函數分析 33
2.3.1鎖相迴路雜訊分析 33
2.3.2鎖相迴路之穩定性分析 36
第三章 三百五十億赫茲鎖相迴路電路實現 41
3.1參考頻率預除器 41
3.2相位頻率檢測器 42
3.3電流幫浦 45
3.4迴路濾波器與迴路頻寬設計 46
3.5電壓控制振盪器 49
3.6除頻器設計 56
3.7真單相時脈除二除三與靜態除二除三除頻器設計 59
3.8注入鎖定式除頻器設計 60
3.9三角積分調變器 67
第四章 模擬結果 84
4.1相位頻率比較 86
4.2電流幫浦 90
4.3壓控振盪器操作頻帶與相位雜訊 93
4.4 CML四個相位波形輸出 95
4.5三角積分調變器與除頻器除數 96
4.6迴路模擬 98
4.7佈局考量 100
第五章 量測計畫 103
第六章 結論 107

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