近年來，針對低功耗終端裝置，許多研究提出了基於脈衝神經網路 (SNN) 的高效能硬體，這類硬體研究集中在實現預訓練模型的推論功能；然而，預訓練模型無法適應不斷變化的環境，因此需要使用本地資料進行重新訓練，神經網絡的訓練需要大量高精度的運算，對於具有功耗限制的終端裝置來說，執行訓練過程是相對困難的，此外，如果將用戶資料上傳雲端伺服器進行重新訓練，可能會有安全及隱私的疑慮。
因此，本論文提出了一個基於卷積SNN的高效能學習系統，該系統可以有效率地執行空間時間反向傳播 (STBP) 演算法，首先，我們針對STBP演算法提出了四個改善方案，使其更容易被硬體實現，且可以達到比原始演算法更高的準確性、更少的脈衝數量和更簡單的反向傳播運算；此外，我們將STBP演算法的浮點數運算量化為低精度整數運算，以在不影響模型準確性的情況下，最小化硬體實現成本；最後，基於改良的STBP演算法，我們提出了一個整合三個訓練階段 (前向、反向及權重更新) 的硬體架構，可以有效地處理整個STBP演算法，利用前向和反向運算的輸入資料稀疏性，減少整體運算能耗和延遲，此架構還具有高度可擴展性，可以組合多個核心支援更寬更深的SNN模型。
我們使用40奈米製程實作了基於該架構的晶片，量測結果顯示，在90％的輸入資料稀疏性下，此晶片可以達到的訓練與推論每瓦每秒運算效率分別為3TOPS/W和7.7TOPS/W，以及達到每個突觸運算僅1.89pJ/SOP的能耗；我們也開發了一個包含多個晶片的系統，我們使用此系統進行SNN訓練，在MNIST資料集上達到了99.1％的準確性，且在SVHN和CIFAR10資料集上展示了首個晶片上訓練的結果，此外，此系統的能源效率比典型商用GPU平台的能源效率平均高了36倍。

In recent years, there has been extensive research on energy-efficient spiking neural network (SNN) hardware for low-power end-point devices. Most hardware studies are about inference-only engines, but the pre-trained models cannot adapt to changing environments. Therefore, there is a growing need for re-training with locally collected data. Training neural networks requires high numerical precision and computing power, so it is arduous for end-point devices with constrained power budgets to perform the training process. In addition, it is also unsuitable and insecure to disclose sensitive user data for cloud-based re-training.
Therefore, this dissertation introduces an energy-efficient convolutional SNN learning system incorporating the scalable hardware architecture and the spatio-temporal back-propagation (STBP) algorithm. We modify the STBP algorithm using four hardware-based enhancing schemes to attain higher accuracy, lower spike counts, and more simple back-propagation compared with the original STBP algorithm. We also convert floating-point operations of the STBP algorithm to low-bitwidth integer operations, in order to minimize hardware costs without sacrificing classification accuracy. Building upon the modified STBP algorithm, we propose a unified hardware architecture encompassing three data-flow modes, i.e., the \emph{forward}, \emph{backward}, and \emph{update} modes, to efficiently process the entire algorithm. Additionally, the architecture exploits input sparsity for both forward and backward computations to reduce the overall processing energy and delay. It also provides multi-core scalability to accommodate wider and deeper models in a multi-core system.
A 40-nm prototype chip has been implemented, achieving peak training and inference efficiencies of 3TOPS/W and 7.7TOPS/W, respectively, at 90\% input sparsity and an energy per synaptic operation (SOP) metric of 1.89pJ/SOP. Based on the chip, our multi-core prototype system achieves a competitive accuracy of 99.1\% on MNIST. We also present the first on-chip training results on SVHN and CIFAR10, demonstrating an average of 36$\times$ improvement in efficiency compared with a typical commercial GPU platform.

摘要------------------------------------------------------------------------------------------------------------------v
Abstract--------------------------------------------------------------------------------------------------------------vii
致謝------------------------------------------------------------------------------------------------------------------ix
List of Figures-------------------------------------------------------------------------------------------------------xv
List of Tables--------------------------------------------------------------------------------------------------------xvii
1 Introduction--------------------------------------------------------------------------------------------------------1
2 Background and Related Work-----------------------------------------------------------------------------------------7
3 An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural Networks-----------------------------31
4 A Low-Bitwidth Integer-STBP Algorithm for Efficient Training and Inference of Spiking Neural Networks---------------47
5 A 40-nm 1.89-pJ/SOP Scalable Convolutional Spiking Neural Network Learning Core with On-Chip STBP-------------------65
6 Conclusions and Future Work-----------------------------------------------------------------------------------------105
Bibliography----------------------------------------------------------------------------------------------------------111

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