極化碼為近年來廣泛討論之錯誤更正碼且是目前唯一能夠被嚴格證明能達到香農極限，而列表連續消除解碼演算法有較好的解碼性能因而被採用在5G通訊之增強型行動寬頻通訊中。而列表連續消除解碼排程為循序解碼，需耗費多個時脈週期做運算，使得解碼器吞吐量非常低。因此本文提出了一局部排序之單一奇偶校驗組成碼節點來減少硬體複雜度與時脈週期也將較可靠的 Rate-1 組成碼改用SC解碼器解碼來減少時脈週期。另外也針對路徑度量值做正規化，使得路徑度量值的量化位元數能夠減少，進而使位在臨界路徑上的排序電路延遲能變短，以提升解碼的操作頻率。而在路徑記憶體中也由直接寫入架構改進為位移式架構以減少大量的硬體複雜度。因此基於這些改善技巧，本文所提出架構可以達到 470~MHz 與 5.26~mm$^{2}$ 在 TSMC 90nm 製成下，相較於先前文獻有較低的面積與較高的吞吐量面積比。

Polar codes have been widely discussed in the recent years and have been proven to achieve the Shannon capacity.
The successive cancellation list (SCL) decoding algorithm have been adopted in control channel for the enhanced mobile broadband (eMBB) scene of the 5G communication.
The SCL decoding is a sequential decoding schedule, and hence, it is difficult to achieve high throughput.
This paper proposed a local sorter of SPC consistent code to reduce hardware costs and cycle counts for Fast-SSCL.
According to the analysis result of the channel reliability, the reliable Fast-SSCL Rate-1 consistent code decoding which has higher reliability than other consistent codes can use low-complexity decoding to reduce the cycle counts.
Besides, the path metric normalization is used to reduce the number of quantization bits and hence the operation frequency can significantly increase.
For the path memory, the direct-write architecture is replaced by shifted-based architecture to reduce hardware costs.
Based on the proposed techniques, this paper proposed a decoder architecture which can achieve 470 MHz and 5.26 mm$^{2}$ synthesized by a TSMC 90 nm CMOS process.
Compared with the previous design, this work has lower area and high throughput to area ratio (TAR) than previous papers.

1 簡介...1
1.1 動機...1
1.2 論文架構...3
2 背景回顧...4
2.1 極化碼編碼...4
2.2 SCL解碼演算法...5
2.3 SCL解碼器回顧...9
2.3.1 解碼器系統架構...9
2.3.2 解碼器各子電路實作...10
3 提出之SCL硬體架構...19
3.1 單一奇偶校驗組成碼局部排序...20
3.2 SC解碼使用在高可靠度的Rate-1節點...23
3.3 路徑度量正規化...25
3.4 位移式路徑位元記憶體架構...28
3.5 硬體結果比較...30
4 結論...34

[1] A. Balatsoukas-Stimming, M. B. Parizi, and A. Burg, “LLR-based successive cancellation list decoding of polar codes,” IEEE Transactions on Signal Processing, vol. 63, no. 19, Oct. 2015.
[2] E. Arikan, “Channel polarization: A method for constructing capacity-achieving codes for symmetric binary-input memoryless channels,” IEEE Transactions on Information Theory, vol. 55, no. 7, pp. 3051-3073, July 2009.
[3] E. Sasoglu, E. Telatar, and E. Arikan, “Polarization for arbitrary discrete memoryless channels,” in 2009 IEEE Information Theory Workshop, pp. 144-148,
Oct. 2009.
[4] C. Berrou, A. Glavieux, and P. Thitimajshima, “Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1,” IEEE International Conference on Communications, vol. 2, pp. 1064-1070 vol.2, May 1993.
[5] R. Gallager, “Low-density parity-check codes,” IRE Transactions on Information Theory, vol. 8, no. 1, pp. 21-28, Jan. 1962.
[6] C. Leroux, A. J. Raymond, G. Sarkis, and W. J. Gross, “A semi-parallel successive-cancellation decoder for polar codes,” IEEE Transactions on Signal Processing, vol. 61, no. 2, pp. 289-299, Jan. 2013.
[7] I. Tal and A. Vardy, “List decoding of polar codes,” in IEEE International Symposium on Information Theory Proceedings, pp. 1-5, Jul. 2011.
[8] K. Niu and K. Chen, “CRC-aided decoding of polar codes,” IEEE Communications Letters, vol. 16, no. 10, pp. 1668-1671, Oct. 2012.
[9] I. Tal and A. Vardy, “List decoding of polar codes,” IEEE Transactions on Information Theory, vol. 61, no. 5, pp. 2213-2226, May 2015.
[10] B. Yuan and K. K. Parhi, “Architecture optimizations for BP polar decoders,” in IEEE International Conference on Acoustics, Speech and Signal Processing (CASSP), pp. 2654-2658, May 2013.
[11] C. Zhang, B. Yuan, and K. K. Parhi, “Reduced-latency SC polar decoder architectures,” in IEEE International Conference on Communications (ICC), pp. 3471-3475, Jun. 2012.
[12] C. Zhang and K. K. Parhi, “Low-latency sequential and overlapped architectures for successive cancellation polar decoder,” IEEE Transactions on Signal Processing, vol. 61, no. 10, pp. 2429-2441, May 2013.
[13] B. Yuan and K. K. Parhi, “Low-latency successive-cancellation polar decoder architectures using 2-bit decoding,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 4, pp. 1241-1254, Apr. 2014.
[14] A. Alamdar-Yazdi and F. R. Kschischang, “A simplified successive-cancellation decoder for polar codes,” IEEE Communications Letters, vol. 15, no. 12, pp. 1378-1380, Dec. 2011.
[15] G. Sarkis and W. J. Gross, “Increasing the throughput of polar decoders,” IEEE Communications Letters, vol. 17, no. 4, Apr. 2013.
[16] G. Sarkis, P. Giard, A. Vardy, C. Thibeault, and W. J. Gross, “Fast polar decoders: Algorithm and implementation,” IEEE Journal on Selected Areas in Communications, vol. 32, no. 5, May 2014.
[17] A. Balatsoukas-Stimming, A. J. Raymond, W. J. Gross, and A. Burg, “Hardware architecture for list successive cancellation decoding of polar codes,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 8, Aug. 2014.
[18] J. Lin and Z. Yan, “An efficient list decoder architecture for polar codes,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 11, Nov. 2015.
[19] Y. Fan, C. Xia, J. Chen, C. Tsui, J. Jin, H. Shen, and B. Li, “A low-latency list successive-cancellation decoding implementation for polar codes,” IEEE Journal on Selected Areas in Communications, vol. 34, no. 2, Feb. 2016.
[20] J. Lin, C. Xiong, and Z. Yan, “A high throughput list decoder architecture for polar codes,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 6, Jun. 2016.
[21] B. Yuan and K. K. Parhi, “LLR-based successive-cancellation list decoder for polar codes with multibit decision,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 1, Jan. 2017.
[22] S. A. Hashemi, C. Condo, and W. J. Gross, “A fast polar code list decoder architecture based on sphere decoding,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 12, Dec. 2016.
[23] S. A. Hashemi, C. Condo, and W. J. Gross, “Fast and flexible successive-cancellation list decoders for polar codes,” IEEE Transactions on Signal Processing, vol. 65, no. 21, Nov. 2017.
[24] R. Mori and T. Tanaka, “Performance and construction of polar codes on symmetric binary-input memoryless channels,” in IEEE International Symposium on Information Theory, pp. 1496-1500, Jun. 2009.
[25] C. J. G. Berhault, C. Leroux and D. Dallet, “Partial sums generation architecture for successive cancellation decoding of polar codes,” in IEEE Signal Processing Systems (SiPS), pp. 407-412, Oct. 2013.
[26] J. L. C. Xiong and Z. Yan, “Symbol-decision successive cancellation list decoder for polar codes,” IEEE Transactions on Signal Processing, vol. 64, no. 3, Feb. 2016.
[27] B. Y. C. Zhang and K. K. Parhi, “Reduced-latency SC polar decoder architectures,” in IEEE International Conference on Communications (ICC), pp. 3471-3475, Jun. 2012.