隨著科技的進步，人類的日常生活越來越依賴科技產品，在這些便利的應用背後，類比數位轉換器是系統中不可或缺的，它能夠將大自然中的類比訊號轉換成數位訊號，使電路能夠進一步利用資訊完成目的。
現今的訊號處理皆以數位訊號處理為主，由於其高可靠度與易實現等特性，漸漸的取代了部分的類比電路，但類比訊號仍是使用者所能感受並操作的，且不同的傳輸模式須要不同的訊號傳輸型態，故做數位訊號處理時，需要對訊號做數位與類比的轉換。
數位類比轉換器會影響訊號發送路徑上的雜訊比以及訊號品質，若有多個頻率同時傳輸資料時，其數位類比轉換器之非理想效應會直接影響信號與信號間的干擾程度，亦會影響整顆元件在競爭上的優勢。且類比數位轉換的過程中，常常遇到時脈抖動與雜訊等問題，因此如何克服這些困難以產生正確的輸出訊號提供後方數位訊號處理電路進行運算便是類比數位轉換器成功於否的關鍵。
現今有許多不同類型的類比數位轉換器被提出以應付不同需求，其中連續漸進式類比數位轉換器是較為流行的，因為它能夠在製程優化的同時獲得更多的優勢。
本論文實現了一個具雜訊整形之連續漸進式類比數位轉換器，在每秒五千萬次取樣的速度下，這個7位元連續漸進式類比數位轉換器利用台積電65奈米的CMOS製程來設計，操作電壓為1.2V。

With new technological advances, people have relied on technology products more and more in daily life. The analog-to-digital converter (ADC) is indispensable in the convenient application. The ADC can convert the analog signal in real life into digital signal, which can be used in the electric circuit to reach the goal.
The signal processing is mainly based on digital signal. Due to high reliability and easy realization, digital circuits gradually replace some analog circuits. However, analog signal is more intuitive to use and different transmission modes require different types of data. Thus, signal must be converted from analog to digital or from digital to analog while applying signal processing.
The ADC has an influence on SNR and quality of the signal on data path. The non-ideal effects of ADC also affect the interference between signals which transmitted at different frequency, which degrades the advantage of the chip. Also, the clock jitter and noise are common in the process of converting. Solving these problem to provide correct signal to followed digital signal processing circuits is the key to build a good ADC.
Many types of ADC are presented to meet the requirement. The Successive-Approximation (SAR) ADC is relatively popular for the reason that it has advantage when the process improves.
This thesis provides a 7-bit SAR ADC with noise shaping of which the sampling rate is 50 million samples per second. It is implemented in a TSMC 65 nm CMOS process with 1.2V supply voltage.

中文摘要 I
Abstract(英文摘要) II
目錄 III
圖目錄 VI
第一章 簡介 1
1.1 研究動機(Motivation) 1
1.2 論文章節組織 2
第二章 研究背景以及相關研究介紹 3
2.1 奈奎斯特取樣類比數位轉換器 3
2.1.1 連續漸進式類比數位轉換器(SAR ADC) 4
2.1.2 管線式類比數位轉換器(Pipeline ADC) 5
2.1.3 快閃式類比數位轉換器(Flash ADC) 7
2.2 類比數位轉換器參數 8
2.2.1 專有名詞 8
2.2.1.a 解析度(Resolution) 8
2.2.1.b 取樣率(Sampling Rate) 8
2.2.1.c 量化誤差(Quantization Error) 8
2.2.1.d 最小解析度(Least Significant Bit) 10
2.2.2 靜態特性 11
2.2.2.a 偏差(Offset) 11
2.2.2.b 增益誤差(Gain Error) 11
2.2.2.c 差動非線性度(Differential Nonlinearity) 12
2.2.2.d 積分非線性度(Integral Nonlinearity) 13
2.2.2.e 遺失碼(Missing Codes) 14
2.2.3 動態特性 14
2.2.3.a 訊號與雜訊比(Signal-to-Noise Ratio) 14
2.2.3.b 訊號與雜訊諧波比(Signal-to-Noise and Distortion Ratio) 14
2.2.3.c 有效位元數(Effective Number of Bits) 15
2.2.3.d 無雜訊動態範圍(Spurious Free Dynamic Range) 15
2.2.3.e 動態範圍(Dynamic Range) 15
2.2.3.f 總諧波失真(Total Harmonic Distortion) 16
2.3 連續漸進式類比數位轉換器(SAR ADC) 16
2.3.1 電荷重新分布SAR ADC(Charge Redistribution SAR ADC) 16
2.3.2 電容切換演算法 17
2.3.2.a 傳統式電容切換演算法(Conventional switching algorithm) 18
2.3.2.b 單調性電容切換演算法(Monotonic switching algorithm ) 19
2.3.2.c 電容拆半切換演算法(Split-capacitor switching algorithm) 21
2.3.3 單端與雙端概念 23
2.3.4 同步與非同步概念 23
2.4 雜訊整形(Noise Shaping) 25
2.4.1 奈奎斯特取樣轉換器與超取樣轉換器性能之比較 25
2.4.2 雜訊整形 25
2.4.3 一階三角積分調變器 27
2.4.4 二階三角積分調變器 28
第三章 具雜訊整形之連續漸進式類比數位轉換器之設計 29
3.1主架構 29
3.2 連續漸進式類比數位轉換器(SAR ADC) 30
3.2.1 取樣及保持電路(Sample and Hold) 30
3.2.1.a 電路原理 30
3.2.1.b 設計考量 30
3.2.1.c 電路實作 34
3.2.2 比較器(Comparator) 36
3.2.2.a 電路原理 36
3.2.2.b 設計考量 36
3.2.2.c 電路實作 37
3.2.3 電容矩陣(Capacitor Array) 39
3.2.4 連續漸進式邏輯電路(SAR Logic) 40
3.2.4.a 內部時序邏輯(Timing Logic) 40
3.2.4.b 控制邏輯(Control Logic) 41
3.3 交換電容積分器 43
3.3.1 對於寄生電容不敏感之延遲型積分器(Parasitic-Insensitive Delay Integrator) 43
3.3.1.a 電路原理 43
3.3.1.b 積分器動態行為 45
3.3.2 運算放大器 46
3.3.2.a 電路原理 46
3.3.2.b 運算放大器非理想效應 48
3.3.3 時脈產生器 53
3.3.4 電路雜訊考量 53
3.3.4.a 熱雜訊 53
3.3.4.b 電晶體閃爍雜訊(Flicker noise) 53
3.3.4.c 離散時間積分器電路之雜訊 54
第四章 模擬結果 57
第五章 結論與未來發展 63
參考文獻 64

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