為了達到更高密度以及更低成本的記憶體，三維NAND型快閃記憶體 (3D NAND) 的技術已經是產品市場上的重點關注對象。3D NAND的基本概念是往垂直方向去堆疊記憶體單元來達到單位面積上有更高的記憶體密度。然而快閃記憶體架構從二維轉換到三維時，會有新型態的讀寫干擾發生在記憶體中。
在這篇論文裡，我們提出針對3D NAND的錯誤模型和測試演算法。首先我們根據3D NAND的幾何架構，把傳統的2D NAND錯誤模型衍生成針對3D NAND的錯誤模型。然後我們提出針對新的讀寫干擾的3D NAND錯誤模型。基於現存的二維快閃記憶體錯誤模擬器RAMSES-FT，我們發展新的快閃記憶體錯誤模擬器RAMSES-3DFT，能夠支援3D NAND錯誤模型，以及支援March概念的測試演算法模擬。我們提出兩個測試演算法來進行3D NAND測試，一個是使用March概念的測試演算法，稱為March-3DFT，另一個是使用Diagonal概念的測試演算法，稱為Diagonal-3DFT。實驗結果顯示我們提出的兩種測試演算法對3D NAND錯誤模型都有好的效果和效率。最後我們相信這篇論文所做的研究能對未來三維 NAND 型快閃記憶體的錯誤模型、錯誤模擬器以及測試演算法的發展做出幫助。

The 3D NAND flash memory technology has attracted significant attention because of the demand for high-density and low-cost storage in the market. The basic idea of 3D NAND flash memory is to stack cells in the vertical dimension to achieve higher density per area. However, because the memory geometric structure changes from 2D to 3D, new types of program disturbance and read disturbance faults appear in 3D NAND flash memories.
In this thesis, we propose fault models and test algorithms for 3D NAND flash memories. First, we extend the traditional 2D NAND fault models to 3D NAND fault models, taking the geometric structure of 3D NAND into account. In addition, we propose new program disturbance and read disturbance fault models for 3D NAND. Based on the existing fault simulator for 2D flash memories, called RAMSES-FT, we develop RAMSES-3DFT to support the simulation of March-like test algorithms for 3D NAND fault models. We propose a March-like test algorithm, called March-3DFT, and a diagonal test algorithm, called Diagonal-3DFT, to test 3D NAND flash memories. Experimental results show that the proposed test algorithms can detect the proposed fault models effectively and efficiently. We believe that the works in this thesis pave the way for future studies of the fault models, fault simulators and test algorithms for 3D NAND flash memories.

中文摘要 i
Abstract ii
Contents iii
Chapter 1 Introduction 1
1.1 Motivation and Objective 1
1.2 Thesis Organization 3
Chapter 2 Background 4
2.1 3D NAND Flash Cell 4
2.2 3D NAND Flash Architectures 4
2.2.1 BiCS (Bit Cost Scalable) 6
2.2.2 P-BiCS (Pipe-Shaped BiCS) 10
2.2.3 TCAT (Terabit Cell Array Transistor) 12
2.3 3D NAND Flash Disturb 14
2.3.1 Program Disturb 15
2.3.2 Read Disturb 17
Chapter 3 Proposed 3D NAND Fault Model 18
3.1 3D NAND Flash Memory Fault Models 18
3.1.1 Word-Line Disturbance Fault (WPD and WED) 19
3.1.2 Bit-Line Disturbance Fault (BPD and BED) 21
3.1.3 3D NAND Program Disturbance Fault (PD_XY, PD_Y) 23
3.1.4 3D NAND Read Disturb Fault (RD_3D) 26
3.1.5 Other NAND Flash Fault Models 27
3.2 Conventional RAM Fault Models 28
Chapter 4 RAMSES-3DFT: A Fault Simulator for 3D NAND Flash Testing 29
4.1 Previous Work (RAMSES-FT) 29
4.2 RAMSES-3DFT 31
4.2.1 3D NAND Flash Structure Parameters 31
4.2.2 Fault Descriptors for 3D NAND 33
4.2.3 Fault Simulating Strategy and Fault Classification for 3D NAND 34
4.3 Fault Coverage Scaling 35
4.3.1 March Algorithm Scale Factor (TC = 1) 37
4.3.2 March Algorithm Scale Factor (TC > 1): PD_XY and RD_3D 44
Chapter 5 Proposed Test Algorithms: March-3DFT and Diagonal-3DFT 52
5.1 March-like Test for 3D NAND Flash (March-3DFT) 52
5.2 Diagonal 3D NAND Flash Test Algorithm (Diagonal-3DFT) 53
5.2.1 Previous Work (Diagonal-FT) 53
5.2.2 Diagonal Plane for 3D NAND 57
5.2.3 Diagonal Test Algorithm 60
5.3 Test Complexity and Fault Coverage 64
5.4 Discussion 67
Chapter 6 Conclusions and Future Work 69
6.1 Conclusions 69
6.2 Future Work 69
Bibliography 70

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