無線通訊技術大幅改善人們的生活，4G通訊提供了極高的資料傳輸速度，讓人們在通話時能有更高的品質甚至透過視訊面對面通話，而在這些美好的應用背後，類比數位轉換器是系統中不可或缺的，它是唯一能夠將大自然訊號轉換成數位訊號的電路。現今許多不同類型的類比數位轉換器持續提升效能，但是連續漸進式類比數位轉換器卻是最近較為流行的，因為它能夠藉由製程縮小獲得更多的優勢。
本論文實現了一個高速帶冗餘位連續漸進式類比數位轉換器，在每秒一點六億次取樣的速度下，使用了帶冗餘位演算法的概念以及數位邏輯上的優化，達到速度上的提升。再透過指叉式電容的使用縮小電容矩陣的面積，並降低容值減少耗能。動態邏輯的應用不但提升了速度，也因為電晶體的數量減少而縮小了面積。此類比數位轉換器具有高速度、低面積的特性，可以用於時序交錯式的類比數位轉換器，透過通道並聯的特性，達到速度上的提升。
這個10位元連續漸進式類比數位轉換器利用台積電65奈米的CMOS製程來設計，操作電壓為1.2V，軌對軌輸入訊號的振幅為1.8V，模擬結果中訊號與雜訊諧波比可達到62.15dB，相當於有效位元為10.029，DNL為+0.01/-0.01LSB，INL為+0.04/-0.04 LSB，平均消耗功率為3.28mW，電路面積約為90μm×189μm = 0.01701mm2；將數位電路簡化後的平均功耗降為1.851mW，電路面積為74μm×178μm = 0.01317mm2。

The development of Wireless communication technology has greatly improved our lives. 4G communication systems provide high data transmission speeds. It allows people to communicate with high-quality voice or even video calls. Behind the amazing applications, the high speed ADC is an essential block in the system. It’s the only block that can convert the nature signal to digital signal. There many types of ADC keep improving their ability. But the SAR ADC is more popular in recent years, because it takes a lot of advantage of technology scales.
In the thesis, we have proposed a high speed SAR ADC. It combined the redundancy algorithm and the optimization of digital circuit to speed up the conversion. Metal-finger capacitors has smaller capacitance. Then, the area of DAC array can be scaled down and the power consumption can be improved. Application of dynamic logic make ADC become faster. It also make the area smaller then static logic because of less transistors. This ADC has high speed performance and low area cost. It can be applied to Time-interleaved ADC. The operation speed will be enhance by channel shunting.
The 10 bits SAR ADC is implemented in a TSMC 65 nm CMOS process with 1.2V supply voltage. The full rail-to-rail input swing is 1.8V peak to peak. This design achieve signal to noise and distortion ratio of 62.15dB, equivalent to the effective number of bits 10.029.The peak DNL values are -0.01 to +0.01 LSB and the peak INL values are -0.04to +0.04 LSB. The average power consumption is 3.28mW. The area is 90μm×189μm = 0.01701mm2. After digital circuit simplification, the average power consumption becomes 1.851mW and the area becomes 74μm×178μm = 0.01317mm2.

中文摘要 i
Abstract(英文摘要) ii
目錄 iii
圖目錄 vi
表目錄 x
第一章 簡介 1
1.1 研究動機(Motivation) 1
1.2 論文章節組織 2
第二章 研究背景以及相關研究介紹 3
2.1 類比數位轉換器參數 3
2.1.1 專有名詞 3
2.1.1.a 取樣率(Sampling Rate) 3
2.1.1.b 解析度(Resolution) 3
2.1.1.c 最小解析度(Least Signification Bit) 3
2.1.1.d 量化誤差(Quantization Error) 4
2.1.2 靜態特性 5
2.1.2.a 偏差(Offset) 5
2.1.2.b 增益誤差(Gain Error) 6
2.1.2.c 差動非線性度(Differential Nonlinearity) 6
2.1.2.d 積分非線性度(Integral Nonlinearity) 7
2.1.2.e 遺失碼(Missing Codes) 8
2.1.3 動態特性 8
2.1.3.a 訊號與雜訊比(Signal-to-Noise Ratio) 8
2.1.3.b 訊號與雜訊諧波比(Signal-to-Noise and Distortion Ratio) 9
2.1.3.c 有效位元數(Effective Number of Bits) 9
2.1.3.d 無雜訊動態範圍(Spurious Free Dynamic Range) 9
2.1.3.e 動態範圍(Dynamic Range) 9
2.1.3.f 總諧波失真(Total Harmonic Distortion) 10
2.2 電荷重新分佈SAR ADC之操作原理 10
2.3 電容切換演算法 12
2.3.1 傳統式電容切換演算法(Conventional switching algorithm) 14
2.3.2 單調性電容切換演算法(Monotonic switching algorithm ) 16
2.3.2 電容拆半切換演算法(Split-capacitor switching algorithm) 17
2.3.4 共模切換演算法(Merged-Capacitor switching algorithm) 18
2.3.5 單向電容切換演算法(Bi-direction switching algorithm) 20
第三章 高速類比數位轉換器設計技術 23
3.1 帶冗餘位演算法 23
3.1.1 基本概念 23
3.1.2 非二進位搜索 (Sub-Radix-2 Search) 25
3.1.2.a 電容不匹配 γ1 26
3.1.2.b DAC穩定時間 γ2 27
3.1.2.c M的選定 28
3.1.3 外加式數位修正 (ADEC) 29
3.1.4 容錯範圍(Error Tolerance Range) 29
3.2 DAC參考電壓限制 30
3.3 數位控制電路的簡化 32
第四章 帶冗餘位連續漸進式類比數位轉換器之設計 36
4.1 取樣及保持電路(Sample and Hold) 36
4.1.1 電路原理 36
4.1.2 設計考量 37
4.1.2.a 頻寬(Bandwidth) 37
4.1.2.b 非線性電阻(Non-linear Resistance) 38
4.1.2.b 熱雜訊(Thermal noise) 40
4.1.2.c 電荷注入效應(Charge injection) 40
4.1.2.d 時脈饋入效應(Clock feedthough) 41
4.1.2.e 孔徑誤差/取樣時間誤差(Aperture Error/Aperture Jitter) 42
4.1.3 電路實作 43
4.1.4 模擬結果與佈局圖 45
4.2 比較器(Comparator) 47
4.2.1 電路原理 47
4.2.2 設計考量 50
4.2.2.a 操作速度(Speed) 50
4.2.2.b 偏移(Offset) 51
4.2.2.c 準確度(Accuracy) 52
4.2.2.d 回饋雜訊(Kick-back noise) 52
4.2.3 電路實作 54
4.2.4 模擬結果 59
4.3 電容矩陣(Capacitor Array) 60
4.3.1 電容選擇 60
4.3.1.a 金屬-絕緣層-金屬電容(Metal-Insulator-Metal Capacitor , MIM Cap) 60
4.3.1.b 金屬-氧化層-金屬電容(Metal-Oxide-Metal Capacitor ,MOM Cap) 61
4.3.2 電容大小 63
4.3.3 電路矩陣 65
4.3.4 電路佈局與模擬結果 67
4.4 數位邏輯控制電路(SAR Logic) 69
4.5 參考電源供應緩衝器(Reference Supply Buffer) 76
4.6 連續漸進式類比數位轉換器(SAR ADC) 效能與佈局 81
第五章 結論與未來發展 87
參考文獻 88

[1] J. McCreary and P. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques,” IEEE J. Solid-State Circuits, vol. 10, no. 6, pp. 371–379, Dec. 1975.
[2] B. P. Ginsburg and A.P. Chandrakasan "An energy-efficient charge recyclingapproach for a SAR converter with capacitive DAC", Proc. IEEE Symp. Circuits Syst., pp.184 -187 2005
[3] C.C. Liu, et al, ‘‘A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,’’ IEEE J. Solid-State Circuits, vol.45, no. 4, Apr. 2010, pp. 731-740.
[4] B. P. Ginsburg and A. P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739-747, Apr. 2007.
[5] Hariprasath, V., et al. "Merged capacitor switching based SAR ADC with highest switching energy-efficiency." Electronics Letters 46.9 (2010): 620-621.
[6] Sanyal, Arindam, and Nan Sun. "An energy-efficient low frequency-dependence switching technique for SAR ADCs." IEEE Transactions on Circuits and Systems II: Express Briefs 61.5 (2014): 294-298.
[7] Wei, Hegong, et al. "A 0.024 mm 2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS." Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International. IEEE, 2011.
[8] Lee, Chun C., and Michael P. Flynn. "A SAR-assisted two-stage pipeline ADC." IEEE Journal of Solid-State Circuits 46.4 (2011): 859-869.
[9] T. Ogawa, H. Kobayashi, Y. Takahashi, N. Takai, M. Hotta, H. San, T. Matsuura, A. Abe, K. Yagi, T. Mori, "SAR ADC Algorithm with Redundancy and Digital Error Correction", IEICE Trans. Fundamentals, vol.E93-A, no.2 (Feb. 2010).
[10] B. Murmann, “On the use of redundancy in successive approximation A/D converters,” in Proc. IEEE Int. Conf. Sampling Theory and Applications (SampTA), 2013, pp. 1–4
[11] Chang, Albert Hsu Ting. Low-power high-performance SAR ADC with redundancy and digital background calibration. Diss. Massachusetts Institute of Technology, 2013.
[12] Cho, Sang-Hyun, et al. "A 550-µW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction." IEEE Journal of Solid-State Circuits 46.8 (2011): 1881-1892.
[13] Liu, Chun-Cheng, et al. "A 10b 100MS/s 1.13 mW SAR ADC with binary-scaled error compensation." Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International. IEEE, 2010.
[14] Shuo-Wei Michael Chen et al, “A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13 μm CMOS” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp.2669-2680, DECEMBER 2006
[15] Zhu, Yan, et al. "A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS." IEEE Journal of Solid-State Circuits 45.6 (2010): 1111-1121.
[16] Tsai, Jen-Huan, et al. "A 1-V, 8b, 40MS/s, 113µW charge-recycling SAR ADC with a 14µW asynchronous controller." VLSI Circuits (VLSIC), 2011 Symposium on. IEEE, 2011.
[17] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599–606, May 1999.
[18] D. Aksin, M. Al-Shyoukh, and F. Maloberti, "Switch Bootstrapping for Precise Sampling Beyond Supply Voltage", IEEE Journal of Solid State Circuits, pp. 1938-1943, Aug.2006.
[19] Huang, Guanzhong, and Pingfen Lin. "A fast bootstrapped switch for high-speed high-resolution A/D converter." Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on. IEEE, 2010.
[20] Chen, Hongmei, et al. "A high-performance bootstrap switch for low voltage switched-capacitor circuits." Radio-Frequency Integration Technology (RFIT), 2014 IEEE International Symposium on. IEEE, 2014.
[21] Fiedler, Horst L., et al. "A 5-bit building block for 20 MHz A/D converters." IEEE Journal of Solid-State Circuits 16.3 (1981): 151-155.
[22] Kobayashi, Tsuguo, et al. "A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture." IEICE transactions on electronics 76.5 (1993): 863-867.
[23] Van Elzakker, Michiel, et al. "A 10-bit Charge-Redistribution ADC Consuming 1.9µW at 1 MS/s." IEEE Journal of Solid-State Circuits 45.5 (2010): 1007-1015.
[24] Pelgrom, Marcel JM, Aad CJ Duinmaijer, and Anton PG Welbers. "Matching properties of MOS transistors." IEEE Journal of solid-state circuits 24.5 (1989): 1433-1439.
[25] Nuzzo, Pierluigi, et al. "Noise analysis of regenerative comparators for reconfigurable ADC architectures." IEEE Transactions on Circuits and Systems I: Regular Papers 55.6 (2008): 1441-1454.
[26] Figueiredo, Pedro M., and Joao C. Vital. "Kickback noise reduction techniques for CMOS latched comparators." IEEE Transactions on Circuits and Systems II: Express Briefs 53.7 (2006): 541-545.
[27] Harpe, Pieter, et al. "A 0.7 V 7-to-10bit 0-to-2MS/s flexible SAR ADC for ultra low-power wireless sensor nodes." ESSCIRC (ESSCIRC), 2012 Proceedings of the. IEEE, 2012.
[28] Harpe, Pieter JA, et al. "A 26uW 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios." IEEE Journal of Solid-State Circuits 46.7 (2011): 1585-1595.
[29] Omran, Hesham, Hamzah Alahmadi, and Khaled N. Salama. "Matching properties of femtofarad and sub-femtofarad MOM capacitors." IEEE Transactions on Circuits and Systems I: Regular Papers 63.6 (2016): 763-772.
[30] Le Dortz, Nicolas, et al. "22.5 A 1.62 GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS." Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International. IEEE, 2014.
[31] Tsai, Jen-Huan, et al. "A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching." IEEE Journal of Solid-State Circuits 50.6 (2015): 1382-1398.