全數位式鎖相迴路相較於傳統式與數位式鎖相迴路，有著更好的雜訊容忍度，隨著先進製程的演進，電路晶片設計可更容易跟隨著製程一起縮小面積。
本論文提出一震盪頻率為4.825GHz具三角積分調變除法器之量化雜訊消除之基於時間數位轉換器浮點數型全數位式鎖相迴路，其中時間數位轉換器電路設計採用基於連續漸進式類比數位轉換器之全新架構設計，其高時間解析度可大幅提升輸出頻譜之相位雜訊表現。
數位濾波器之電路設計採用左移/右移(Left/Right Shifter)電路取代乘法器以大幅降低晶片面積並透過Scan Chain電路設計以大幅提升迴路鎖定時間。
於數位控制震盪器採用二階三角積分調變器以大幅降低數位類比轉換器之量化雜訊對輸出頻譜的影響，於壓控震盪器則採用切換式電容以調變電容電感式壓控震盪器之震盪頻率範圍。最後透過十六位元三階三角積分調變器以調變除法器達成所需之除數解析度，透過以上子電路建構出完整的全數位式鎖相迴路電路架構。
論文開頭以簡介各種鎖相迴路基本架構並進行比較，接著依序講解全數位式鎖相迴路之數學模型、設計流程並進行各子電路雜訊分析以分析晶片規格，最後採用台積電65奈米製程技術進行實體電路架構分析、模擬佈局與晶片下線考量，並以本篇論文設計進行統合性的結論，整體系統晶片功耗為17.40768mW、晶片總面積為1.07 mm X 0.78 mm。

All-Digital Phase-Locked Loop have better noise tolerance than Conventional & Digital Phase-Locked Loop. With the evolution of advanced process, circuit design can scale down with the process more easily.
We propose a 4.825GHz Fractional-N TDC-Based All-Digital Phase-Locked Loop w/i Sigma-Delta Modulator Noise Cancellation in this thesis. The circuit design of Time to Digital Converter is based on a Successive Approximation Analog to Digital Converter (SAR ADC). The brand new architecture design of TDC can significantly increase the phase noise performance of output spectrum by its high time resolution.
The circuit design of Digital Loop Filter is implemented by Left/Right Shifter circuit instead of Multiplier circuit to significantly reduce the chip area and greatly accelerate the locking time of system through the Scan Chain circuit design.
The Digital Control Oscillator is implemented by a second-order sigma-delta modulator to reduce the effect of DAC quantization noise on the output spectrum. As the Voltage Control Oscillator, switched capacitor tuning banks are used to modulate the tuning range of LC tank VCO. The desired divisor resolution of divider is modulated by sixteen-bit third-order sigma-delta modulator in the end. The above sub-circuits construct a complete All-Digital Phase-Locked Loop circuit architecture.
This thesis begins from a brief introduction and comparison to various kinds of basic Phase-Locked Loop architecture. Then explains the mathematical model and design flow of All-Digital Phase-Locked Loop sequentially. Besides, the noise analysis of each sub-circuits is performed to analyze the system specifications.
Finally, the physical circuit architecture analysis, layout considerations and Pre/Post simulations is implemented by the TSMC 65nm process. Then concludes the complete circuit design in this thesis. The overall system power consumption is 17.40768mW, and the total system area is 1.07 mm X 0.78 mm.

摘要 i
Abstract ii
目錄 iii
圖目錄 iv
表目錄 vii
第一章 序論 1
1.1 研究動機 1
1.2 論文章節介紹 2
第二章 鎖相迴路系統架構介紹 3
2.1 簡介 3
2.2 傳統數位式鎖相迴路 3
2.3 全數位式鎖相迴路 11
2.4 鎖相迴路架構優缺點比較 18
第三章 全數位鎖相迴路系統分析 20
3.1 系統穩定度分析 20
3.2 相位雜訊分析 25
第四章 電路設計與實現 32
4.1 簡介 32
4.2 時間數位轉換器電路設計 33
4.3 數位濾波器電路設計 45
4.4 數位控制震盪器電路設計 50
4.5 三角積分調變多除數除法器與量化雜訊消除電路設計 58
第五章 佈局規劃與模擬結果 67
5.1 時間數位轉換器模擬結果 67
5.2 數位迴路濾波器模擬結果 68
5.3 三角積分調變數位類比轉換器模擬結果 69
5.4 壓控震盪器模擬結果 71
5.5 三角積分調變除法器與雜訊消除電路模擬結果 73
5.6 系統迴路模擬結果與晶片佈局 76
第六章 結論 78
6.1 總結 78
6.2 未來展望 78
6.3 參考文獻 80

[1] Staszewski, Robert Bogdan, and Poras T. Balsara. All-digital frequency synthesizer in deep-submicron CMOS. John Wiley & Sons, 2006.
[2] Perrott, Michael H., Mitchell D. Trott, and Charles G. Sodini. "A modeling approach for/spl Sigma/-/spl Delta/fractional-N frequency synthesizers allowing straightforward noise analysis." IEEE Journal of Solid-State Circuits 37.8 (2002): 1028-1038.
[3] Tavakol, A. "Digitally Controlled Oscillator for WiMAX in 40 nm." (2012).
[4] Hsu, Chun-Ming. Techniques for high-performance digital frequency synthesis and phase control. Diss. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2008.
[5] C. M. Hsu, M. Z. Straayer, and M. H. Perrott, "A Low-Noise Wide-BW 3.6-GHz Digital $DeltaSigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation," IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2776-2786, 2008.
[6] Miller, Brian, and Bob Conley. "A multiple modulator fractional divider." Frequency Control, 1990., Proceedings of the 44th Annual Symposium on. IEEE, 1990.
[7] Z. Wang, C. Huang, and J. Wu, "An ADPLL with a MASH 1-1-1 ΔΣ Time-digital converter," in MELECON 2014 - 2014 17th IEEE Mediterranean Electrotechnical Conference, 2014, pp. 266-270.
[8] R. Gu and S. Ramaswamy, "Fractional-N phase locked loop design and applications," in 2007 7th International Conference on ASIC, 2007, pp. 327-332.
[9] W. Rhee, "Design of high-performance CMOS charge pumps in phase-locked loops," in Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on, 1999, vol. 2, pp. 545-548 vol.2.
[10] A. Elkholy, T. Anand, W. S. Choi, A. Elshazly, and P. K. Hanumolu, "A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC," IEEE Journal of Solid-State Circuits, vol. 50, no. 4, pp. 867-881, 2015.
[11] J. Chen, S. Jia, and Y. Wang, "A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier," in 2015 IEEE 11th International Conference on ASIC (ASICON), 2015, pp. 1-4.
[12] H. Molaei, A. Khorami, and K. Hajsadeghi, "A wide dynamic range low power 2× time amplifier using current subtraction scheme," in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 462-465.
[13] X. Gao et al., "9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, ???246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS," in 2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, pp. 174-175.
[14] Z. Xu, M. Miyahara, K. Okada, and A. Matsuzawa, "A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC," IEEE Journal of Solid-State Circuits, vol. 51, no. 10, pp. 2345-2356, 2016.
[15] Henzler, Stephan. Time-to-digital converters. Vol. 29. Springer Science & Business Media, 2010.
[16] 劉深淵，楊清淵，《鎖相迴路》。滄海書局，2006。
[17] 高曜煌，《射頻鎖相迴路IC設計》。滄海書局，2005。
[18] Behzad Razavi著，李峻霣譯，《類比CMOS 積體電路設計(修訂版)》。東華書局，2013。