此篇論文提出應用混合式自動重送請求(hybrid automatic repeat request)機制之硬體友善的5G低密度奇偶檢查(low-density parity-check)解碼排程。因為在奇偶檢驗矩陣(parity-check matrix)中有內建的穿刺區塊，此特性會造成解碼時間變長，為了減少解碼所需的迭代次數，我們分別針對第一次解碼、使用Chase合併(Chase combining)的混合式自動重送請求，和使用增量冗餘(incremental redundancy)的混合式自動重送請求提出較有效率的解碼排程。我們提出的排程能夠在第一次解碼中，根據穿刺沿的數量進行排程，能夠有效率的先復原穿刺節點後，再接續後面的解碼運算。在使用Chase合併的混合式自動重送請求時，我們保留穿刺部分的前次解碼結果，並根據列權重進行排程。在使用增量冗餘的混合式自動重送請求時，我們先傳送對應到奇偶檢驗矩陣中純列正交(pure-row-orthognal)部分的奇偶位元。根據硬體實現的結果，當碼率為0.303時，在第一次解碼中的吞吐量可以增加21.37%，在Chase合併之混合式自動重送請求下可增加56.9%，而在增量冗餘之混合式自動重送請求下可增加14.51%。

This paper presents hardware-friendly LDPC decoding schedules for 5G hybrid automatic repeat request (HARQ) applications. Since there are built-in punctured blocks in the parity check matrix (PCM), a scheduling technique is proposed that allows the punctured nodes to be efficiently recovered. For HARQ using the Chase combining (CC), the previous decoding results corresponding to the punctured part are retained, and the proposed layered decoding is arranged according to the row weight. For HARQ using the incremental redundancy (IR) approach, the parity bits corresponding to the pure-row-orthogonal part of the PCM are transmitted first. The hardware implementation shows that the throughput can be increased by 21.37% for the first decoding attempt, 56.9% for CC-HARQ and 14.51% for IR-HARQ when the code rate reaches 0.303.

第一章 簡介..................................................... 1
第二章 初步準備................................................. 4
第一節 5G碼率兼容之低密度奇偶檢查編碼........................... 4
第二節 混合式自動重送請求機制................................... 6
第三節 基於標準化之最小值-總和演算法的分層式低密度奇偶檢查碼.... 8
第三章 提出的高效率分層解碼排程................................. 11
第一節 5G低密度奇偶檢查的解碼排程............................... 11
第二節 應用混合式自動重送請求機制之5G低密度奇偶檢查碼的解碼排程. 14
一、Chase合併之混合式自動重送請求............................... 14
二、增量冗於之混合式自動重送請求................................ 16
第四章 低密度奇偶檢查解碼器硬體架構............................. 19
第一節 基本硬體模組設計......................................... 21
一、Q/Λ更新器.................................................. 21
二、標準化...................................................... 21
三、找小值...................................................... 22
第二節 硬體實作挑戰............................................. 23
一、旋轉位移器.................................................. 23
二、提早終止器.................................................. 25
三、取餘數...................................................... 28
第三節 提出的排程方法之硬體設計................................. 30
第五章 結論..................................................... 32

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