近幾年神經網路被認為是推動人類智慧的重要推手，可是使用傳統的計算機架構進行運算的速度過慢，因此許多研究在研發新的硬體架構供神經網路使用。而電阻式隨機存取記憶體可以用來加速神經網路，因為此架構可以模仿人類大腦運作方式，將記憶與執行計算的功能在同一個記憶單元上完成，但記憶體可能因為製程偏移造成記憶體有缺陷，並使神經網路的可靠度下降。實驗結果顯示若是在記憶體陣列裡10%的記憶單元損壞，MLP的辨識率會下降10%，LeNet 300-100和LeNet 5的辨識率都下降超過65%。為了解決這個問題，首先，我們整理出記憶體內的所有錯誤的種類，並設計模擬器驗證測試演算法是否可以偵測所有錯誤的種類。此外，我們提出自我修復與錯誤更正的方法避免神神網路的辨識率大幅下降，並提升神經網路的壽命。 實驗結果顯示，如果神經網路下降幅度在5%內，MLP使用錯誤更正的方法可以容忍40%的錯誤在記憶體陣列裡，LeNet 300-100和LeNet 5則可以容忍高達60%。此外，使用錯誤更正的方法可以多延長硬體5%的壽命。比較兩種方法，錯誤更正的方法是更有效的，因為使用自我修復並加上備援記憶體的效能仍舊無法像只用錯誤更正的方法來得好。

Neural network (NN) has been considered as an important factor for the success of many AI applications. As the von Neumann architecture is inefficient for NN computation, researchers have been investigating new semiconductor devices and architectures for neuromorphic computing. The crossbar RRAM, which is an emerging non-volatile memory composed of memristor devices, can be used to accelerate or emulate the NN computation. Using memristors can achieve memorizing and computing on the same cell, which is the same architecture as human brain. However, the memristor device defects exposed during manufacturing or field use may cause performance degradation in the NN, causing reliability issues to the neuromorphic hardware. In this work, we summarize the fault model and design fault simulator for crossbar multi-level RRAM. Besides, we consider two existing fault models for the 1T1R RRAM cell, i.e., the stuck-at fault and transistor stuck-on fault. We simulate 3 kinds of models on MNIST data set, which contains grey scale hand written digits, from 0 to 9. Evaluation of the faults effect on the NN shows that for about 10% faulty cells in the memristor array, the accuracy for the MLP (Multi-layer perception) model degrades about 10%, and that for the LeNet 300-100 and LeNet 5 degrades by more than 65%. Therefore, we propose a self-healing and an error correction approach to reduce the accuracy degradation, and improve the reliability (lifetime) of the neuromorphic hardware. Our simulation results show that if we limit the accuracy degradation to within 5%, then the proposed self-healing approach for the MLP model will be able to tolerate up to 20% faulty cells, and up to 40% faulty cells for LeNet 300-100 and LeNet 5 models. On the other hand, proposed error correction approach for the MLP model will be able to tolerate up to 40% faulty cells, and even up to 60% faulty cells for LeNet 300-100 and LetNet 5 models. Also, the error correction method can extend the lifetime of the neuromorphic hardware by 5% for the MLP model and 10% for LeNet 300-100 and LeNet 5 models. Finally, we compare the chips after repaired by spare rows/columns, error correction is more powerful than self-healing, because the self-healing with redundancy still tolerate less faults than error correction without redundancy.

摘要 i
Abstract ii
List of Figures v
List of Tables vi
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Related Work 2
1.3 Proposed Approach 3
1.4 Thesis Organization 4
Chapter 2 Background 5
2.1 Multi-level Crossbar RRAM Architecture 5
2.2 Fully Connected Layer 8
2.3 Convolutional Layer 9
Chapter 3 Multi-level RRAM Fault Simulator 11
3.1 Crossbar RRAM Fault Model 11
3.2 Multi-level RRAM Fault Descriptors 15
Chapter 4 Proposed Approach for Improving Neural Network Reliability 18
4.1 Self-Healing 18
4.2 Error Correction 23
Chapter 5 Experimental Results 25
5.1 Apply March Test Algorithm on Fault Simulator 25
5.2 Accuracy Comparison between Self-Healing and Error Correction 28
5.3 Repair Resource Comparison 30
5.4 Life Time Evaluation 34
Chapter 6 Conclusion and Future Work 37
6.1 Conclusion 37
6.2 Future Work 38
Bibliography 39

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