在多種新穎應用的，包括自動駕駛汽車，協作機器人等，電子系統的功能安全性和可靠性變得更加關鍵。在功能安全性或可靠性設計的方面，錯誤模擬被用於分析電子系統中，錯誤的發生以及這些錯誤對於系統整體的影響。然而在實際的使用層面上，錯誤模擬往往需要耗費大量資源來完成系統的功能性，這些功能性模擬所要求的模擬可能需要數十萬或是數百萬個週期，來完成所有的功能應用的模擬。同樣，更複雜的電路設計也導致系統中有越來越多的錯誤的候選位置需要進行模擬，這些原因都造成了功能性故障模擬所需要消耗的時間與資源。這篇論文提出了一種減少功能性故障模擬中，待測錯誤數量的方法。這個方法基於對模擬中的電路暫存器進行ACE位元區域的分析，而這些位於相同ACE區間的ACE位元候選（故障）在傳遞時可能具有相同的故障行為。具有相同故障效果的ACE位元會在模擬過程中被迫棄，以進一步減少功能性故障模擬中真正需要進行模擬的錯誤數量。在方法的實作中，我們對每個電路進行動態模擬追蹤，以分析功能性模擬中，這些RTL電路設計中的 ACE 位元狀態。並且，我們透過建立並使用電路圖形來分析錯誤的傳遞效果以減少並對錯誤效果進行分類與篩選並大量減少最終ACE位元的數量。實驗結果表明在平均上，該方法可以減少 PicoRV32 CPU 內核中，架構暫存器六成以上 ACE 位元數量。其餘四成的待測錯誤中約有九成可以進一步得藉由比較錯誤效果來進行排除。因為具有相同錯誤行為的ACE位元可以通過利用一個代表性錯誤進行模擬。

Functional safety and reliability of electronic systems become more critical for several novel applications including autonomous car, collaboration robots, etc. For functional safety or reliability design, error simulation is essential in analyzing the influence of faulty behavior in a system. In practice, the simulation takes much time to simulate the functionality for all cycles in an application. Also more complex designs result in the growing number of the faulty candidate locations. In this thesis, we proposed an fault reduction method to reduce the fault number for the functional error simulation. The method is based on the analysis of ACE bit regions, in which ACE candidate bits (faults) may have same error behavior at the end of the region. ACE bits with the same error patterns will be collapsed without further simulation efforts. In the implementation, we instruments each circuit for the dynamic simulation trace to analyze the ACE bits in the RTL design during the functional simulation. And we use a circuit graph to analyze faulty effects for reduction comparison.Thus, we can reduce the number of the final ACE bits significantly.The experiment results show that there is a ~60% reduction of the total ACE bits of architecture registers in the PicoRV32 CPU core on average. And about 90% of the remaining 40% faults can be further excluded because multiple faults on ACE bits which show an equivalent faulty behavior can be grouped and characterized by a single representative fault.

摘要
致謝
目錄
1 Introduction----------------------------------8
1.1 Objective and Motivation----------------------8
1.2 Thesis Organization---------------------------9
2 Background------------------------------------10
2.1 Related Work----------------------------------10
2.2 Architecturally Correct Execution (ACE)-------11
2.3 Neo4j Graph Database--------------------------12
2.4 Verilator HDL Simulator-----------------------12
2.5 Overall Fault Reduction Method----------------13
3 Circuit Graph---------------------------------15
3.1 Propagation Path------------------------------15
3.2 Parse RTL Design------------------------------18
3.2.1 Propagation Path in Verilog and SystemVerilog-19
3.2.2 Verilator Abstract Syntax Tree----------------20
3.3 Build Circuit Graph---------------------------23
3.3.1 Walk Abstract Syntax Tree---------------------23
3.3.2 Propagation Path Management-------------------24
3.3.2.1 Database Structure Mapping--------------------24
4 Dynamic Simulation Trace----------------------26
4.1 Assignment Identification---------------------26
4.2 Tracer Instrumentation------------------------27
5 Automatic ACE Evaluation----------------------28
5.1 Identification of Signal State----------------28
5.1.1 Propagation Path Inquiry----------------------29
5.1.2 Destination and Source Signals on Path--------31
5.1.3 Path Match with Assignment Log----------------32
5.2 ACE bits Evaluation---------------------------33
6 Fault Reduction-------------------------------36
6.1 Fault Injection Wrapper-----------------------36
6.2 Fault Location in ACE Interval----------------37
6.3 Fault Effect Classification-------------------38
7 Experimental Result---------------------------40
7.1 Test Circuit----------------------------------40
7.2 Fault Reduction Result------------------------41
7.2.1 PicoRV32--------------------------------------41
7.2.1.1 Dhrystone, Cycle Count = 18,909---------------41
7.2.1.2 Qsort, Cycle Count = 4,754--------------------43
7.2.2 Pulpino---------------------------------------45
7.2.2.1 Qsort, Cycle Count = 5,453--------------------45
7.2.3 MD5-------------------------------------------47
8 Conclusions and Future Work-------------------49
8.1 Conclusions-----------------------------------49
8.2 Future Work-----------------------------------50

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