可靠度測試是電子產品上市前的重要測試，在數種可靠度測試中溫度循環負載測試模擬每次產品使用時溫度上升，關機時溫度回到室溫的過程，根據JEDEC標準測試規範，常用的溫度測試範圍為-40°C到125°C，以極端的測試環境達到減少測試時間的目的，但即使是以極端溫度環境進行測試，測試過程也經常需要一個月的測試時間。因此以有限單元法模擬測試條件的方式，可以達到加速產品開發時程，降低開發成本。
對有限單元靜力分析而言，有限單元法所使用的單元尺寸(Element)對模擬結果有相當程度的影響，尤其在應力應變集中區域單元尺寸尤其要謹慎規劃，目前預估封裝壽命的方式對於應變有高敏感度，因此需要尋找適用的單元尺寸，並加以定義，以取得可靠的封裝壽命預估。
現今高性能的電子產品大多採用球柵陣列封裝(Ball Grid Array)，而扇出型封裝因應I/O數量增加與晶片的小型化而越來越常被使用。另一方面玻璃基板因為其熱膨脹係數與矽晶圓相近，能解決封裝中因為基板與晶片的熱膨脹係數不匹配導致翹曲，進而造成無法進一步加工的問題。
本研究將針對錫球材料的非線性行為，包含彈性行為、塑性行為、潛變與Chaboche動態硬化模型來模擬在溫度循環負載中錫球材料的變形。主要目標是找到適用於WLCSP(Wafer Level Chip Scale Packaging)在溫度循環測試三維模擬中所適用的單元尺寸，並搭配Coffin-Manson法得到封裝的平均破壞時間。倘若所得到之封裝壽命，與實際實驗值相符合，可以說此單元尺寸是適用於溫度循環測試模擬。當相同的模擬方式經過足夠的實驗驗證，有限單元模擬將可取代部分實驗。
本研究將根據上述認證後之單元尺寸來探討I/O墊片尺寸對扇出型封裝結構之可靠度影響。

Reliability testing is an important phase before the marketing of electronic products. In several reliability tests, the temperature cycle load test simulates the temperature rise during each use of the product and then returning back to the room temperature during shutdown. According to the JEDEC standard, the commonly used temperature test range is -40 ° C to 125 ° C, with the ultimate test environment to reduce test time purposes. But even in extreme temperature environments, the testing process often takes a month for testing. Therefore, the method of simulating the test conditions by the finite element method can accelerate the product development schedule, to reduce the development cost.
For finite element static analysis, the element size used in the finite element method has a considerable influence on the simulation results. In particular, the cell size in the stress-strain concentrated area should be carefully planned. The way of estimating the package lifetime is Strain has high sensitivity, so need to find the applicable element size, and to define, in order to obtain a reliable estimate of the package life expectancy.
Most of the high-performance electronic products nowadays use Ball Grid Array, and because of the increasing demand in more number of I/O and the miniaturization of the chip, fan-out packages are being used. On the other hand, the coefficient of thermal expansion of glass substrate is similar to that of the silicon wafer, thus it could resolve the warpage caused by CTE mismatch in the package, and the manufacturing process could proceed without issues.
In this study, the deformation of the solder balls in a temperature cycling load is simulated according to the nonlinear behaviour of the solder ball material, including elastic behaviour, plastic behaviour, creep and Chaboche dynamic hardening model. The main goal of this research work is to find out an optimal element size that is suitable for use in temperature cycling test simulations and to find the mean time to failure of package using Coffin-Manson method. If the resulting package life is consistent with the actual experimental value, it could be said that the element size is suitable for temperature cycling test simulation. Finite element simulations will replace some of the experiments when the same simulation method has been sufficiently validated.
This study will investigate the effect of I/O pad size on the reliability of fan-out package structures based on the above-identified element size.

摘要 …………………………………………………………………...I
Abstract ………………………………………...……………………….III
目錄 .…………………………………………………………………...V
表目錄 ………………………………………………………………...VII
圖目錄 ...…………………………………………………………......VIII
第一章 緒論 2
1.1 研究動機 2
1.2 文獻回顧 3
1.3 研究目標 5
第二章 基礎理論 7
2.1 錫球外型預測 7
2.2 有限元素法基礎理論 9
2.2.1 線彈性有限元素理論 10
2.2.2 材料非線性理論 14
2.2.3 潛變變形機制 18
2.2.4 Garofalo-Arrhenius 潛變模型 19
2.2.5 Anand 模型 20
2.2.6 數值方法及收斂準則 22
2.3 硬化法則 24
2.3.1 等向硬化法則 24
2.3.2 動態硬化法則 25
2.3.3 潛變理論 26
2.4 Chaboche 模型 27
2.5 封裝結構可靠度之預測方法 29
2.5.1 Coffin-Manson 應變法 29
2.5.2 Darveaux 能量密度法 30
2.5.3 修正型能量密度法 31
第三章 Fan-Out WLCSP溫度負載實驗有限單元模型建立 32
3.1 有限單元模型基本假設 32
3.2 WLCSP於溫度負載測試實驗 32
3.2.1 有限單元模型建立 32
3.2.2 材料參數設定 41
3.2.3 邊界條件設定 42
3.2.4 溫度負載設定 43
第四章 結果分析與討論 46
4.1 模型結構差異比較 46
4.2 壽命預估公式 47
4.3 WLCSP 在塑性下模擬結果分析 48
4.3.1 實驗與有限元素模型驗證 48
4.3.2 Pure plastic 模擬結果 51
4.4 WLCSP 在潛變下模擬結果分析 52
4.4.1實驗與有限元素模型驗證 53
4.4.2 Modify Energy-base method 公式模擬結果 55
4.5模擬結果比較 56
4.6 封裝結構參數化分析 57
第五章 結論與未來工作 62
參考文獻 63

[1] M. C. Hsieh. “Modeling Correlation for Solder Joint Fatigue Life Estimation in Wafer-Level Chip Scale Packages,” International Microsystems, Packaging, Assembly and Circuits Technology Conference, Taipei, Taiwan, Oct. 21-23,2015.
[2] L. S. Goldmann. “Geometry Optimization of Controlled Collapse Interconnections,” IBM Journal of Research and Development, Vol. 13, No. 3, pp. 251-265, 1969.
[3] S. M. Heinrich, M. Schaefer, S. A. Schroeder, and P. S. Lee. “Prediction of Solder Joint Geomertry on Array-Type Interconnections,” American Society of Mechanical Engineers Journal of Electronic Packaging, Vol. 118, pp. 114-121, 1996.
[4] K. A. Brakke. “Surface Evolver Manual,” version 2.01, Minneapolis: The Geometry Center, 1996.
[5] C. M. Liu, C. C. Lee, and K. N. Chiang. "Enhancing the Reliability of Wafer Level Packaging by using Solder Joints Layout Design," IEEE Transactions on Component and Packaging Technologies, vol. 29, No. 4, pp. 877-885, 2006
[6] L. F. Coffin. “A Study of the Effects of Cyclic Thermal Stress on a Ductile Metal,” Transactions on American Society of Mechanical Engineers, Vol. 76, pp. 931-950, 1954.
[7] K. C. Wu, S. Y. Lin and T. Y. Hung. “Reliability Assessment of Packaging Solder Joints Under Different Thermal Cycle Loading Rates,” IEEE Transactions on Device and Materials Reliability, vol. 15, No. 3, pp. 437-442, 2015.
[8] R. Darveaux. “Effect of Simulation Methodology on Solder Joint Crack Growth Correlation and Fatigue Life Prediction,” Journal of Electronic Packaging, Vol. 124, pp. 147-154, 2002.
[9] K. J. Bathe. “Finite Element Procedures in Engineering Analysis,” New Jersey: Prentice Hall, 1982.
[10] S. Timoshenko. “ Theory of Elasticity,” Auckland: Mcgraw-Hill College, 1970.
[11] J. Lau, W. Danksher, and P. Vianco. “Acceleration Models, Constitutive Equations, and Reliability of Lead-Free Solders and Joints,” Electronic Components and Technology Conference, Proceedings 53rd, New Orleans, LA, USA, May 27-30, 2003.
[12] W. N. Findley, J. S. Lai, and K. Onaran. “Creep and Relaxation of Nonlinear Viscoelastic Materials, with an Introduction to Linear Viscoelasticity,” Amsterdam: North-Holland, 1976.
[13] R. D. Cook, D. S. Malkus, M. E. Plesha, and R. J. Witt. “Concepts and Applications of Finite Element Analysis,”New York: Wiley, 2001
[14] J. Chakrabarty. “Theory of Plasticity,” Burlington: Elsevier, 2006.
[15] N. E. Dowling. “Mechanical Behavior of Materials,” New Jersey: Prentice-Hall, 1999.
[16] Dieter, George E. “Mechanical Metallurgy,” London :McGraw Hill, 1988.
[17] J. L. Chaboche. “Constitutive equations for cyclic plasticity and cyclic viscoplasticity,” International Journal of Plasticity, Vol. 5, No. 3, pp. 247-302, 1989.
[18] J. L. Chaboche. “On Some Modifications of Kinematic Hardening to Improve the Description of Ratchetting Effects,” International Journal of Plasticity, Vol. 7, No. 7, pp. 661-678, 1991.
[19] L. F. Coffin. “A Study of the Effects of Cyclic Thermal Stress on a Ductile Metal,” New York: Knolls Atomic Power Laboratory, 1953.
[20] R. Darveaux. “Effect of Simulation Methodology on Solder Joint Crack Growth Correlation and Fatigue Life Prediction,” Journal of Electronic Packaging, Vol. 124, pp. 147-154, 2002.
[21] M. Motalab, M. Mustafa, J. C. Suhling, J. Zhang, J. Evans, M. J. Bozack and P. Lall. “Thermal Cycling Reliability Predictions for PBGA Assemblies That Include Aging Effects,” International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, San Francisco, USA, July 16-18, 2013.
[22] H. Ma, and J. Suhling, “A review of mechanical properties of lead-free solders for electronic packaging,” Journal of Materials Science, Vol. 44, No. 5, pp. 1141-1158, 2009.
[23] F. Garofalo, “Fundamentals of creep and creep-rupture in metals,” New York: Macmillan Company, 1965
[24] L. Anand, “Constitutive equations for hot-working of metals,” International Journal of Plasticity, Vol. 1, No. 3, pp. 213-231, 1985.
[25] S. B. Brown, K. H. Kim, and L. Anand, “An internal variable constitutive model for hot working of metals,” International Journal of Plasticity, Vol. 5, No. 2, pp. 95-130, 1989.
[26] 鄒承諺，以修正型能量密度法評估晶圓級封裝之可靠度，國立清華大學動力機械工程學系，碩士論文，2017
[27] Y. J. Xu, L. Q. Wang, F. S. Wu, W. S. Xia, and H. Liu, “Effect of Interface Structure on Fatigue Life under Thermal Cycle with SAC305 Solder Joints,” IEEE Electronic Packaging Technology International Conference, Vol. 15, pp, 959-964, 2013.
[28] J. Chang, L. Wang, J. Dirk, and X. Xie, “Finite Element Modeling Predicts the Effects of Voids on Thermal Shock Reliability and Thermal Resistance of Power Device,” Welding Journal , Vol. 85, No. 3, pp. 63-70, 2006.
[29] 張天寧，具玻璃基板扇出型晶圓級封裝結構參數分析及可靠度評估，國立清華大學動力機械工程學系，碩士論文，2017
[30] B. Rogers and C. Scanlan, "Improving WLCSP Reliability Through Solder Joint Geometry Optimization", International Symposium on Microelectronics, Vol.46, No. 2, pp. 546-550, 2013.
[31] M. C. Hsieh and S.L. Tzeng, "Solder Joint Fatigue Life Prediction in Large Size and Low Cost Wafer-Level Chip Scale Packages," International Conference on Electronic Packaging Technology(ICEPT) , Chengdu, China , May 12-15, 2014.
[32] P. T. Vianco,"Fatigue and Creep of Lead-free Solder Alloys: Fundamental Properties," Chapter 3 Lead-free Solder Interconnect Reliability, Edited by D. Shangguan, ASM International, pp. 67-106, 2006.
[33] M. C. Hsieh,"Modeling Correlation for Solder Joint Fatigue Life Estimation in Wafer-Level Chip Scale Packages," International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), Taipei, Taiwan , Oct 21-23. 2015.
[34] K. M. Chen, K. K. Ho and D. S. Jiang, “Impact Of Lead Free Solder Materials On Board Level Reliability For Low-k WLCSP,” IEEE Electronic Packaging Technology International Conference, Vol. 33, No. 2,pp. 340-347, 2010.
[35] Huann-Wu Chiang, Jun-Yuan Chen, Ming-Chuan Chen, Jeffrey C. B. Lee and Gary Shiau, “Reliability testing of WLCSP lead-free solder joints,” Journal of Electronic Materials, Vol. 35, No.5, pp.1032-1040, 2006.
[36] Ming-Che Hsieh,“Simulations and characterizations for stress reduction designs in wafer level chip scale packages,” International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), Taipei, Taiwan , Oct 22-25. 2013
[37] K. M. Chen, “Lead-Free Solder Material and Chip Thickness Impact on Board-Level Reliability for Low-K WLCSP,” IEEE Electronic Packaging Technology International Conference, Vol. 33, No. 2, pp. 340-347, 2010.