半導體製程中，適當的活化能提升元件電特性、改善界面層品質、降低漏電流等，而合適的佈植深度也能提高汲極電流、減少接面之反向電流，摻雜活化及離子佈植在製程中扮演著至關重要的角色。本論文應用遠紅外光(10.6μm)及綠光(532nm)退火，利用綠光短波長的特性主要活化表層，遠紅外光則活化源汲極深處，期望能改善傳統快速熱退火的缺陷。而雙重離子佈植則是以磷建立較深的接面減少接面漏電流，以砷建立較淺層之接面，提供通道反轉所需的載子。
在論文的第一部分，利用兩種不同波長的雷射退火搭配較低溫的快速熱退火，既可以降低製程的熱預算，進而抑制源極與汲極在摻雜活化後因高溫導致的雜質擴散情形嚴重而造成的漏電，而經過雷射退火後閘極介電層的粗糙度也會變小。實驗結果顯示經過紅外光及綠光雷射退火後，電晶體特性如汲極電流(4.011x10-5 A/μm)、最大轉導值(38.66 μA/V)及次臨界擺幅特性(約68.7 V/dec)，電性比起傳統的熱退火有著顯著的提升。
第二部分，文獻中提到雙重離子佈植法可以提升元件的電特性，因此設計出五個不同的佈植參數來做平面式電晶體。藉由第一次磷的植入對表面的矽進行預先非晶化植入，使得第二次的砷可以建立較淺層的接面，比起單次離子植入能擁有更低的接面漏電流，而臨界電壓的漂移情況也比單次離子植入來的穩定。
延續上一個部分，我們發現雙重離子佈植法有開關特性不佳的缺點，因此在第三部分中，我們挑選幾個較佳的佈植參數應用在SOI-FinFET的結構上，期望藉由SOI基板及鰭式電晶體的優勢，在維持汲極電流的同時大幅降低漏電流。實驗結果發現磷40keV/砷40keV有最佳的汲極電流(6.814 x10-5 A/μm)、開關特性比(1.234 x108 )、最大轉導值(49.36μA/V)，發現在鰭式電晶體的結構上雙重離子佈植法可以進一步提升電流特性。

Electrical characteristics and interface layer quality can be improved, and leakage current can be reduced in FinFET by appropriate activation process. The drain current can be enhanced and reverse current of junction can be decreased by suitable depth of ion implantation. Doping activation and ion implantation always play important roles in electrical characteristics of FinFET. In this thesis, far infrared light(10.6μm) and visible green light(532nm) were used for annealing dopants. The short wavelength of green light is used to activate the surface layer, and the far infrared light is intended to activate deeper region of source-drain. Laser annealing is expected to reduce the defects, which are generally caused by traditional rapid thermal annealing. Double ion implantations include a deep junction with Phosphorus to reduce junction leakage, and a shallow junction with Arsenic to provide sufficient channel carrier at inversion.
On the first part of the thesis, laser annealing with two wavelengths and rapid thermal annealing are applied to the thermal budget of fabrication process, which may suppress leakage current caused by diffusion after high temperature. It is known that the roughness of gate dielectric are less after laser annealing treatment. The experimental results show that the excellent electrical characteristics of FinFET are obtained such as the drain current (4.011x10-5 A/μm), the maximum transconductance value (38.66 μA/V) and the sub-threshold swing characteristics (about 68.7 V/dec) after red and green laser annealing. Electrical properties of FinFET with laser annealing using two wavelengths are much improved as compared to these with traditional thermal annealing.
In the second part, double ion implantations method are studied to increase on current of MOSFET, so five devices with different implantation parameters are designed. The surface is pre-amorphized by Phosphorus implantation, and then the shallow junction is formed by an Arsenic ion implantation. The junction leakage current of device with double ion implantations is lower than that with single one. The variation of threshold voltage with double ion implantations is more stable than that with single one.
The on/off ratio of device with double ion implantations is poor as found in previous part. In the third part, various implantation energy for both shallow and deep dopants on SOI FinFET are investigated to reduce the leakage current and keep large drain current. The results show that FinFET with S/D junction formed by phosphorus 40keV/arsenic 40keV has the highest drain current (6.814 x10-5 A/μm), on/off ratio (1.234 x108), maximum transconductance value (49.36μA/V), it is also found that double ion implantation can further improve the on current characteristics.

摘要 I
ABSTRACT III
致謝 V
目錄 VII
表目錄 X
圖目錄 XI
第一章 緒論 1
1.1 前言 1
1.2 使用HIGH-K 介電材料的原因 1
1.3 高介電材料的選擇 2
1.4 絕緣層覆矽基板 3
1.5 鰭式電晶體 3
1.6 氫氣電漿處理的影響 3
1.7 雷射退火的應用 4
1.8 論文架構 4
第二章 元件製程與量測 15
2.1 氧化鉿及二氧化鈦為介電層應用在GATE FIRST SOI N-FINFET製作流程 15
2.2 電性量測 17
第三章 不同波長雷射活化於絕緣層覆矽鰭式電晶體之電性研究 24
3.1 研究動機 25
3.2 製程與量測 26
3.3實驗結果與討論 28
3.3.1使用不同活化方式在堆疊介電層之SOI N-FINFET之等效電容特性分析 28
3.3.2使用不同活化方式在堆疊介電層之SOI N-FINFET之電晶體特性分析 29
3.3.3使用不同活化方式在堆疊介電層之SOI N-FINFET之可靠度分析 32
3.4結論 32
第四章 不同摻雜離子之雙重離子佈植法於矽平面電晶體之電性研究 46
4.1 研究動機 47
4.2 製程與量測 48
4.3實驗結果與討論 49
4.3.1不同摻雜離子在不同厚度的屏蔽氧化層之結果分析 50
4.3.2使用不同摻雜離子及佈植能量之平面MOSFET在各階段熱製程之電阻特性分析 50
4.3.3使用不同摻雜離子及佈植能量在堆疊介電層之平面MOSFET接面特性分析 52
4.3.4使用不同摻雜離子及佈植能量在堆疊介電層之平面MOSFET電晶體特性分析 53
4.3.5使用不同摻雜離子及佈植能量在堆疊介電層之平面MOSFET電晶體可靠度分析 54
4.4結論 55
第五章 不同摻雜離子之雙重離子佈植法於絕緣層覆矽鰭式電晶體之電性研究 69
5.1 研究動機 69
5.2 製程與量測 70
5.3實驗結果與討論 72
5.3.1使用不同摻雜離子及佈植能量在堆疊介電層之SOI-FINFET電晶體特性分析 72
5.3.2使用不同摻雜離子及佈植能量在堆疊介電層之SOI-FINFET電晶體可靠度分析 73
5.4結論 74
第六章 結論與展望 83
6.1 結論 83
6.2 未來展望 84
參考文獻 86

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