複晶快閃記憶體近來被研究應用在NAND記憶體堆疊上。要如何增加提升操作特性是重要的議題，各種方式如非晶矽結晶、環繞式閘極結構、多晶鍺的使用以及能帶工程等皆被提出。本篇論文中，探討不同電荷捕捉層以及阻擋氧化層處理的多晶矽環繞式閘極元件操作特性。以及多晶鍺通道環繞式閘極快閃記憶體元件之低溫製程研究。
本論文分為幾個部分，第一部分研究氧化鋯摻雜二氧化鈦/氮化矽堆疊形成電荷捕捉層與氧化鋁阻擋氧化層之氮電漿處理之效應在複晶矽環繞式閘極快閃記憶體元件上。由實驗結果氧化鋯摻雜二氧化鈦/氮化矽堆疊之電荷捕捉層，在操作速度上並沒有顯著提高。此外在氧化鋯之電荷捕捉層摻雜二氧化鈦之元件的電荷保持力特性較差。然而在二氧化鋯摻雜鈦之電荷捕捉層之樣品有要較好的耐久力表現。此外，元件之電荷保持力特性在氧化鋁之阻擋氧化層使用氮電漿處理後是有被改善的。推測可能的原因為氮電漿修補/減少之中之缺陷。
第二部分著重在多晶鍺為通道之快閃記憶體的可靠度和介面品質問題。為解決這些問題，較低熱預算製程之應用將具有相當重要的意義。在這部分，採用氧電漿處理和以低溫沉積氧化鋁為隧穿層來處理這問題。根據實驗結果，對可靠度特性有顯著影響，但對操作速度並沒有太大影響。採用氧電漿處理之樣品表現出更好的可靠度特性。
在最後部分，還研究了具有三閘極/環繞式閘極之複晶鍺通道元件的特性。複晶鍺環繞式閘極快閃記體明顯地表現出更快的寫入/擦除速度、較大的記憶窗口、較低的工作電壓和較小的次臨界擺幅。但是環繞式閘極結構仍然有一些缺點，例如較差的耐久力特性。由於環繞式閘極之曲率電場增強效應，可能導致穿隧氧化層在寫入/抹除循環期間更容易受到損傷。氧電漿處理介面應用在多晶鍺環繞式閘極結構，對可靠度特性有顯著改善，但對操作速度沒有影響。

Polycrystalline channel flash memory device has been applied for NAND flash memory devices. How to enhance operating characteristics is important issues. Many approaches have been proposed such as Amorphous-Si crystallization, Gate all around(GAA) structure, polycrystalline germanium(Poly-Ge) and bandgap-engineered dielectrics. In this thesis, operation characteristics of poly-Si GAA device with different charge trapping layers and blocking oxides treatment are studied. Poly-Ge GAA CT flash memory device with low temperature process is also investigated.
The thesis is divided into three parts. In the first part, the effects of trapping layer composed of ZrOx doped TiO2/Si3N4 stack and Al2O3 blocking layer with N2 plasma treatment on poly-Si GAA charge trapping (CT) flash device are investigated. From the experiment results, the operating speeds of the device with ZrOx doped TiO2/Si3N4 stacked trapping layer are not significantly improved. Moreover, the devices with ZrOx trapping layer doped TiO2 show worse retention characteristic. However, it is found that the samples with ZrOx doped Ti trapping layer show better endurance performance. Furthermore, the results indicate that the retention characteristic of the device is improved by N2 treated Al2O3 blocking layer. Probably the reason is the defect in the blocking layer is fixed/reduced by N2 plasma treatment.
The second part focuses on CT flash device with poly-Ge channel, which has the problems of reliability and interfaces quality. To resolve those issues, the application of lower thermal budget process is of considerable importance. In this section, O2 plasma treatment and Al2O3 tunneling layer deposited at low temperature were adopted to approach the problem. According to experiment results, significant improvement of reliability performance is achieved, but the operating speeds are not changed. The samples with O2 plasma treatment evidence show better reliability performance.
In the last section, operation characteristics of poly-Ge device with Tri-Gate/GAA channel are also studied. Poly-Ge CT flash devices with GAA structure exhibit significantly improved performance with higher program/erase speeds, larger memory window, lower operating voltage, and smaller subthreshold swing. But there are still some disadvantages of the GAA structure, such as poor endurance performance. Because of the electric-field enhanced by corner effect, it may lead tunneling layer damaged much easily during P/E operation. As the O2 plasma treatment was performed on poly-Ge CT flash memory with GAA structure, the reliability performance is significantly improved. However, there is no obvious difference in operating speeds.

摘要 i
Abstract ii
致謝 iv
目錄 iv
圖目錄 xi
表目錄 xviii
第一章 序緒論 1
1.1. 非揮發性記憶體 1
1.1.1. 快閃記憶體元件 1
1.1.2. 浮動閘極式快閃記憶體 2
1.1.3. 電荷捕捉式快閃記憶體 3
1.2. 多晶矽薄膜電晶體 5
1.2.1. 低溫複晶矽結晶方法 6
1.3. 多向式閘極結構與奈米線通道式快閃記憶體元件 7
1.4. 高介電係數材料 8
1.4.1. 能帶工程 9
1.5. 無接面式快閃記憶體元件介紹 10
1.6. 矽化鍺與鍺通道的應用 11
1.7. 各章摘要 14
第二章 快閃記憶體元件的製程與操作方法 21
2.1. 主要製程機台原理介紹 21
2.1.1. 原子層沉積系統 21
2.1.2. 感應耦合型電漿化學氣相沉積系統 23
2.2. 快閃記憶體元件實驗樣品製造流程 24
2.2.1. 傳統平面式快閃記憶體元件 24
2.2.2. 奈米線式通道快閃記憶體元件製程 25
2.2.3. 環繞式閘極通道快閃記憶體元件製程 26
2.3. 快閃記憶體元件基本操作原理 28
2.3.1. 載子穿隧機制 28
2.3.2. 福勒-諾德海姆穿隧(Fowler-Nordheim Tunneling) 29
2.3.3. 直接穿隧 (Direct Tunneling) 30
2.4. 快閃記憶體寫入與抹除方法 31
2.4.1. 通道熱電子注入 31
2.4.2. 福勒-諾德海姆穿隧寫入 32
2.4.3. 福勒-諾德海姆穿隧抹除 32
2.5. 快閃記憶體元件可靠度特性 33
2.5.1. 電荷保持力 (Retention) 33
2.5.2. 耐久力 (Endurance) 34
2.6. 快閃記憶體元件之量測方法 35
2.6.1. 快閃記憶體元件基本特性曲線量測方法 35
2.6.2. 快閃記憶體元件寫入與抹除量測方法 35
2.6.3. 快閃記憶體電荷保持力量測方法 36
2.6.4. 元件耐久力量測方法 36
第三章 介電層堆疊電荷捕捉層對多晶矽奈米線通道快閃記憶體元件特性之影響研究 65
3.1. 研究動機與背景 65
3.2. 實驗樣品製作流程與條件 67
3.3. 實驗結果與討論 69
3.3.1. 元件之汲極電流對閘極電壓特性圖 69
3.3.2. 元件寫入與抹除特性 69
3.3.3. 元件可靠度特性 70
3.4. 本章節之結論 71
第四章 低溫成長堆疊穿隧氧化層於多晶鍺快閃記憶體元件操作特性之影響研究 82
4.1. 研究動機與背景 82
4.2. 實驗樣品製作流程與條件 83
4.3. 結果與討論 85
4.3.1. 元件之汲極電流對閘極電壓特性圖 86
4.3.2. 元件寫入與抹除特性 86
4.3.3. 元件可靠度特性 87
4.4. 結論 88
第五章 環繞式閘極對多晶鍺通道快閃記憶體元件操作特性之影響研究 101
5.1. 研究動機與背景 101
5.2. 實驗樣品製作流程與條件 102
5.3. 結果與討論 105
5.3.1. 元件之汲極電流對閘極電壓特性圖 105
5.3.2. 元件寫入與抹除特性 106
5.3.3. 元件可靠度特性 108
5.4. 結論 110
第六章 總結 123
6.1. 結論 123
6.2. 未來展望 124
參考文獻 126

[1] S. M. Sze et al., Physics of semiconductor devices. John wiley & sons, 2006.
[2] M. L. French et al., "Design and scaling of a SONOS multidielectric device for nonvolatile memory applications," IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, vol. 17, no. 3, pp. 390-397, 1994.
[3] K. T. San et al., "Effects of erase source bias on Flash EPROM device reliability," IEEE Transactions on Electron Devices, vol. 42, no. 1, pp. 150-159, 1995.
[4] M. H. White et al., "On the go with SONOS," IEEE Circuits and Devices Magazine, vol. 16, no. 4, pp. 22-31, 2000.
[5] M. H. White et al., "A low voltage SONOS nonvolatile semiconductor memory technology," IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, vol. 20, no. 2, pp. 190-195, 1997.
[6] J. Bu et al., "Retention reliability enhanced SONOS NVSM with scaled programming voltage," in Aerospace Conference Proceedings, 2002. IEEE, 2002, vol. 5, pp. 5-5: IEEE.
[7] D. Kahng et al., "A floating gate and its application to memory devices," Bell Labs Technical Journal, vol. 46, no. 6, pp. 1288-1295, 1967.
[8] T.-Y. Tseng, Nonvolatile memory: materials, devices and applications. American Scientific Publishers, 2012.
[9] N. Yamauchi et al., "Polysilicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film," IEEE Transactions on Electron Devices, vol. 38, no. 1, pp. 55-60, 1991.
[10] S. Jagar et al., "Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization," in Electron Devices Meeting, 1999. IEDM'99. Technical Digest. International, 1999, pp. 293-296: IEEE.
[11] K. Werner, "The flowering of flat displays," IEEE spectrum, vol. 34, no. 5, pp. 40-49, 1997.
[12] M. Stewart et al., "Polysilicon VGA active matrix OLED displays-technology and performance," in Electron Devices Meeting, 1998. IEDM'98. Technical Digest., International, 1998, pp. 871-874: IEEE.
[13] M. K. Hatalis et al., "Large grain polycrystalline silicon by low‐temperature annealing of low‐pressure chemical vapor deposited amorphous silicon films," Journal of applied physics, vol. 63, no. 7, pp. 2260-2266, 1988.
[14] K. Shimizu et al., "High-mobility poly-Si TFT's fabricated by a novel excimer laser crystallization method," IEEE Transactions on Electron Devices, vol. 39, no. 11, pp. 2664-2665, 1992.
[15] C.-L. Wang et al., "High-performance polycrystalline-silicon nanowire thin-film transistors with location-controlled grain boundary via excimer laser crystallization," IEEE Electron Device Letters, vol. 33, no. 11, pp. 1562-1564, 2012.
[16] G.-B. Kim et al., "Electrical characteristics of MILC poly-Si TFTs with long Ni-offset structure," IEEE Transactions on Electron Devices, vol. 50, no. 12, pp. 2344-2347, 2003.
[17] M. S. Haque et al., "Aluminum‐induced crystallization and counter‐doping of phosphorous‐doped hydrogenated amorphous silicon at low temperatures," Journal of applied physics, vol. 79, no. 10, pp. 7529-7536, 1996.
[18] L. Hultman et al., "Crystallization of amorphous silicon during thin‐film gold reaction," Journal of applied physics, vol. 62, no. 9, pp. 3647-3655, 1987.
[19] S. Y. Yoon et al., "Low temperature metal induced crystallization of amorphous silicon using a Ni solution," Journal of applied physics, vol. 82, no. 11, pp. 5865-5867, 1997.
[20] T.-H. Hsu et al., "A high-speed BE-SONOS NAND flash utilizing the field-enhancement effect of FinFET," in Electron Devices Meeting, 2007. IEDM 2007. IEEE International, 2007, pp. 913-916: IEEE.
[21] R. Chau et al., "High-k metal-gate stack and its MOSFET characteristics," IEEE Electron Device Letters, vol. 25, no. 6, pp. 408-410, 2004.
[22] J. Fu et al., "Si-nanowire TAHOS (TaN/Al2O3/HfO2/SiO2/Si) nonvolatile memory cell," in Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European, 2008, pp. 115-118: IEEE.
[23] Y.-N. Tan et al., "Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage layer," IEEE Transactions on Electron Devices, vol. 51, no. 7, pp. 1143-1147, 2004.
[24] M. S. Joo et al., "Formation of hafnium-aluminum-oxide gate dielectric using single cocktail liquid source in MOCVD process," IEEE Transactions on Electron Devices, vol. 50, no. 10, pp. 2088-2094, 2003.
[25] H.-T. Lue et al., "BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability," in Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, 2005, pp. 547-550: IEEE.
[26] Z.-H. Ye et al., "A novel SONOS-type flash device with stacked charge trapping layer," Microelectronic Engineering, vol. 86, no. 7-9, pp. 1863-1865, 2009.
[27] J.-P. Colinge et al., "Junctionless nanowire transistor: complementary metal-oxide-semiconductor without junctions," Science of Advanced Materials, vol. 3, no. 3, pp. 477-482, 2011.
[28] J.-P. Colinge et al., "Nanowire transistors without junctions," Nature nanotechnology, vol. 5, no. 3, p. 225, 2010.
[29] D. K. Schroder, Semiconductor material and device characterization. John Wiley & Sons, 2006.
[30] C.-H. Fu et al., "Enhanced hole mobility and low Tinv for pMOSFET by a novel epitaxial Si/Ge superlattice channel," IEEE Electron Device Letters, vol. 33, no. 2, pp. 188-190, 2012.
[31] S. Maikap et al., "Characteristics of strained-germanium p-and n-channel field effect transistors on a Si (1 1 1) substrate," semiconductor science and technology, vol. 22, no. 4, p. 342, 2007.
[32] L. Weltzer et al., "Enhanced CHISEL programming in flash memory devices with SiGe buried layer," in Non-Volatile Memory Technology Symposium, 2004, 2004, pp. 31-33: IEEE.
[33] D. Kencke et al., "Enhanced secondary electron injection in novel SiGe flash memory devices," in Electron Devices Meeting, 2000. IEDM'00. Technical Digest. International, 2000, pp. 105-108: IEEE.
[34] S. C. Wolfson et al., "Transient simulation to analyze Flash memory erase improvements due to germanium content in the substrate," IEEE Transactions on Electron Devices, vol. 57, no. 10, pp. 2499-2503, 2010.
[35] C.-C. Wang et al., "Enhanced band-to-band-tunneling-induced hot-electron injection in p-channel flash by band-gap offset modification," IEEE electron device letters, vol. 27, no. 9, pp. 749-751, 2006.
[36] L.-J. Liu et al., "Improvement on programming and erasing speeds for charge-trapping flash memory device with SiGe buried channel," Solid-State Electronics, vol. 54, no. 10, pp. 1113-1118, 2010.
[37] S. C. Wolfson et al., "Transient simulation to analyze flash memory programming improvements due to Germanium content in the substrate using Nonquasi-Static techniques," Microelectronic Engineering, vol. 99, pp. 23-27, 2012.
[38] J. H. You et al., "Effect of the trap density and distribution of the silicon nitride layer on the retention characteristics of charge trap flash memory devices," in Simulation of Semiconductor Processes and Devices (SISPAD), 2011 International Conference on, 2011, pp. 199-202: IEEE.
[39] H. Bachhofer et al., "Transient conduction in multidielectric silicon–oxide–nitride–oxide semiconductor structures," Journal of Applied Physics, vol. 89, no. 5, pp. 2791-2800, 2001.
[40] D. H. Kim et al., "Comparative investigation of endurance and bias temperature instability characteristics in metal-Al2O3-nitride-oxide-semiconductor (MANOS) and semiconductor-oxide-nitride-oxide-semiconductor (SONOS) charge trap flash memory," JSTS: Journal of Semiconductor Technology and Science, vol. 12, no. 4, pp. 449-457, 2012.
[41] M. Lenzlinger et al., "Fowler‐Nordheim tunneling into thermally grown SiO2," Journal of Applied physics, vol. 40, no. 1, pp. 278-283, 1969.
[42] Y. Wang et al., "An analytical retention model for SONOS nonvolatile memory devices in the excess electron state," Solid-State Electronics, vol. 49, no. 1, pp. 97-107, 2005.
[43] H. P. Belgal et al., "A new reliability model for post-cycling charge retention of flash memories," in Reliability Physics Symposium Proceedings, 2002. 40th Annual, 2002, pp. 7-20: IEEE.
[44] Y. Kumagai et al., "Statistical evaluation for anomalous SILC of tunnel oxide using integrated array TEG," in Reliability Physics Symposium, 2008. IRPS 2008. IEEE International, 2008, pp. 219-224: IEEE.
[45] T. Kim et al., "Comprehensive understanding on the role of tunnel oxide top nitridation for the reliability of nanoscale flash memory," IEEE Electron Device Letters, vol. 34, no. 3, pp. 396-398, 2013.
[46] M. Bocquet et al., "An in-depth investigation of physical mechanisms governing SANOS memories characteristics," in Memory Workshop, 2009. IMW'09. IEEE International, 2009, pp. 1-4: IEEE.
[47] A. Rothschild et al., "O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory," in Solid State Device Research Conference, 2009. ESSDERC'09. Proceedings of the European, 2009, pp. 272-275: IEEE.
[48] A. Paul et al., "Comprehensive simulation of program, erase and retention in charge trapping flash memories," in Electron Devices Meeting, 2006. IEDM'06. International, 2006, pp. 1-4: IEEE.
[49] A. Fayrushin et al., "Unified endurance degradation model of floating gate NAND Flash memory," IEEE Transactions on Electron Devices, vol. 60, no. 6, pp. 2031-2037, 2013.
[50] Z.-H. Ye et al., "Enhanced Operation in Charge-Trapping Nonvolatile Memory Device With Si3N4/Al2O3/HfO2 Charge-Trapping Layer," IEEE Electron Device Letters, vol. 33, no. 10, pp. 1351-1353, 2012.
[51] M. Bera et al., "Reliability of Ultra-thin Zirconium Dioxide (ZrO2) Films on Strained-Si," in Physical and Failure Analysis of Integrated Circuits, 2006. 13th International Symposium on the, 2006, pp. 295-300: IEEE.
[52] S. Bang et al., "Physical and electrical properties of hafnium–zirconium–oxide films grown by atomic layer deposition," Journal of The Electrochemical Society, vol. 155, no. 9, pp. H633-H637, 2008.
[53] G. D. Wilk et al., "High-κ gate dielectrics: Current status and materials properties considerations," Journal of applied physics, vol. 89, no. 10, pp. 5243-5275, 2001.
[54] J. W. Lim et al., "Electrical properties of alumina films by plasma-enhanced atomic layer deposition," Electrochemical and solid-state letters, vol. 7, no. 8, pp. F45-F48, 2004.
[55] C.-J. Su et al., "A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires," Nanoscale research letters, vol. 7, no. 1, p. 162, 2012.
[56] L.-J. Liu et al., "Enhanced programming and erasing speeds in p-channel charge-trapping flash memory device with SiGe buried channel," IEEE Electron Device Letters, vol. 33, no. 9, pp. 1264-1266, 2012.
[57] P.-C. Huang et al., "Electric-field enhancement of a gate-all-around nanowire thin-film transistor memory," IEEE Electron Device Letters, vol. 31, no. 3, pp. 216-218, 2010.