為了微縮等效氧化層厚度，二氧化鈦和二氧化鋯相比二氧化鉿有較高的介電常數，因此可以用來替代二氧化鉿做為閘極介電層，使電容值上升，鰭式電晶體驅動電流也會有所提升。另外對閘極介電材料做NH3和CF4電漿處理，可以使高介電常數材料的k值提升，使電容上升。但用高介電材料作為閘極介電層會遇到載子遷移率下降的問題，而矽鍺的載子遷移率比矽高，所以在通道材料用矽鍺取代純矽，可以有較高的驅動電流，而矽鍺超晶格通道結構可以把載子侷限在量子井，使載子集中，可以提升載子遷移率，得到較高的驅動電流。
第一部分實驗主要在ALD內成長二氧化鉿以及二氧化鈦作為介電層，藉由二氧化鉿和二氧化鈦的堆疊及對二氧化鉿經過NH3電漿處理來提升整體閘極介電層的k值，來達到抑制等效氧化層厚度的效果。從實驗結果可發現有二氧化鈦和NH3電漿處理的二氧化鉿在閘極堆疊結構之FinFET有較高汲極電流(3.7x10-5A/μm)、轉導值(34.6μA/V)和較低S.S.(約為68.92mV/dec)，且等效氧化層厚度約為1.32nm。而在可靠度的部分，介電層為二氧化鉿經過NH3電漿處理在閘極堆疊的元件有較好的可靠度。
第二部分實驗使用熱穩定性較佳的二氧化鋯來替代二氧化鈦。在疊二氧化鉿完後經過CF4電漿處理可以使驅動電流及電容值變大。從實驗結果可以發現有二氧化鋯在閘極堆疊之FinFET的EOT降低了0.18nm，有CF4電漿處理介電層有較大的汲極電流、轉導值特性，且有較好的S.S.。而可靠度方面，有經過NH3電漿處理的二氧化鉿在閘極堆疊的元件有較好的可靠度。
第三部分實驗主要在改變通道材料，使用Si0.8Ge0.2作為通道材料，其中矽鍺超晶格是用Si0.8Ge0.2/Si/Si0.8Ge0.2的堆疊方式，通道為矽鍺超晶格堆疊方式的樣品和只有矽鍺為通道的樣品相比中間多磊晶一層矽，能使載子侷限在量子井內，以提升載子遷移率及元件電特性。從實驗結果來看不論在PMOS或NMOS在通道為矽鍺超晶格的結構下，都有較高的汲極電流(PMOS：3.62x10-5A，NMOS：6.99x10-5A)和轉導最大值(PMOS：30.15(μA/V)，NMOS：54.25(μA/V))。

Since the dielectric constant k-value of TiO2 and ZrO2 is higher than that of HfO2, HfO2 gate dielectric is replaced with TiO2 and ZrO2 to increase gate capacitance and on current of FinFETs. NH3 and CF4 plasma treatment on high-k gate dielectric also can improve capacitance. However, the carrier mobility degradation may be caused by high-k gate dielectric. The mobility of SiGe is higher than of which silicon. SiGe with superlattice structure can confine the carrier in quantum well to enhance the on current.
In the first part, HfO2 and TiO2 gate dielectric were in-situ deposited by atomic layer deposition (ALD). NH3 plasma is treated on HfO2 to improve the k-value and suppress EOT. It is found out that the gate stack with TiO2 and HfO¬2 with NH3 treatment in FinFETs show higher on current, Gm maximum, and lower subthreshold swing. HfO¬2 with NH3 treatment shows better performance in reliability.
Because the leakage current of TiO2 is much higher than that of the gate stack with HfO2, in the second part, TiO2 is replaced with ZrO2 with better thermal stability. High-k material with CF4 plasma also improves on current and capacitance. It is found out that the EOT of the gate stack with ZrO2 is reduced by 0.18 nm. The devices with CF4 plasma show higher on current, Gm maximum, and lower subthreshold swing.
In the third part, the different channel material is studied. Si0.8Ge0.2 buried channel is epitaxially grown on silicon wafer, since strained SiGe processes higher carrier mobility. There is one silicon layer which can confine the carrier in quantum well between SiGe in the sample of SiGe with superlattice structure. Both the n-FinFET and p-FinFET with SiGe superlattice buried channel show higher on current and Gm maximum.

摘要 i
Abstract iii
致謝 iv
目錄 v
圖目錄 ix
表目錄 xii
第一章 序論 1
1.1 前言 1
1.2 使用High-k介電材料的原因 1
1.3 高介電材料的選擇 1
1.4 緣層覆矽基板 2
1.5 鰭式電晶體 3
1.6 矽鍺虛擬基板-應變通道 3
1.6.1 臨界厚度 4
1.6.2 差排 4
1.7 氫氣電漿處理的影響 5
1.8 論文架構 5
第二章 元件製程與量測 18
2.1 High-K材料為介電層應用在Gate First SOI n-FinFET製作流程 18
2.1.1 晶片刻號 18
2.1.2 鰭式矽通道形成 18
2.1.3 氫氣電漿Trimming矽通道輪廓處理與閘極介電層沉積量測 19
2.1.4 金屬閘電極的形成 19
2.1.5 源極(Source)、汲極(Drain)的形成 19
2.1.6 保護層沉積 19
2.1.7 接出金屬導線、燒結 20
2.2 電性量測 20
2.2.1 電容的量測 20
2.2.2 金氧半電晶體的量測 20
第三章 氧化鉿及氧化鈦介電層結構之NH3電漿處理之電特性研究 27
3.1 研究動機 28
3.2 製程與量測 28
3.2.1 製程流程及條件 28
3.2.2 量測參數 29
3.3 實驗結果與討論 29
3.3.1 元件在穿透式電子顯微鏡下的分析 30
3.3.2 氧化鉿及氧化鈦介電層堆疊對鰭式電晶體相同閘極電容之電特性分析 30
3.3.2.1 電容-電壓量測曲線 30
3.3.2.2 閘極漏電流密度對電壓量測曲線 31
3.3.3 氧化鉿及氧化鈦介電層堆疊對於鰭式電晶體之電特性分析 31
3.3.3.1 汲極電流對閘極電壓量測曲線 31
3.3.3.2 轉導對閘極電壓量測曲線 32
3.3.3.3 汲極電流對電壓量測曲線 32
3.3.4 氧化鉿及氧化鈦介電層堆疊對於鰭式電晶體之可靠度分析 32
3.3.4.1 F-N Stress臨界電壓飄移特性 32
3.3.4.2 F-N Stress對轉導的影響 33
3.4 本章結論 33
第四章 氟電漿處理之氮氧化鉿及氮氧化鋯堆疊對鰭式電晶體電特性研究 42
4.1 研究動機 43
4.2 製程與量測 43
4.2.1 製程流程及條件 43
4.2.2 量測參數 44
4.3 實驗結果與討論 45
4.3.1 元件在穿透式電子顯微鏡下的分析 45
4.3.2 氧化鉿及氧化鋯介電層堆疊對鰭式電晶體相同閘極電容之電特性分析 45
4.3.2.1 CF4電漿條件選擇 45
4.3.2.2 電容-電壓量測曲線 46
4.3.2.3 閘極漏電流密度對電壓量測曲線 46
4.3.3 氧化鉿及氧化鋯介電層堆疊對於鰭式電晶體之電特性分析 46
4.3.3.1 汲極電流對閘極電壓量測曲線 46
4.3.3.2 轉導對閘極電壓量測曲線 47
4.3.3.3 汲極電流對電壓量測曲線 47
4.3.4 氧化鉿及氧化鈦介電層堆疊對於鰭式電晶體之可靠度分析 48
4.3.4.1 F-N Stress臨界電壓飄移特性 48
4.3.4.2 F-N Stress對轉導的影響 48
4.4 本章結論 48
第五章 磊晶矽鍺掩埋通道之鰭式電晶體之電性研究 59
5.1 研究動機與背景 60
5.2 製程與量測 61
5.2.1 製程流程及條件 61
5.2.2 量測參數 63
5.3 實驗結果與討論 63
5.3.1 矽與矽鍺及矽鍺超晶格通道對鰭式電晶體相同閘極電容之電特性分析 63
5.3.1.1 電容-電壓量測曲線 63
5.3.1.2 閘極漏電流密度對電壓量測曲線 63
5.3.2 矽與矽鍺及矽鍺超晶格通道對於鰭式電晶體之電特性分析 64
5.3.2.1 汲極電流對閘極電壓量測曲線 64
5.3.2.2 轉導對閘極電壓量測曲線 64
5.3.2.3 汲極電流對電壓量測曲線 65
5.3.3 矽與矽鍺及矽鍺超晶格通道對於鰭式電晶體之可靠度分析 65
5.3.3.1 F-N Stress臨界電壓飄移特性 65
5.3.3.2 F-N Stress對轉導的影響 65
5.4 本章結論 65
第六章 結論與展望 79
6.1 結論 79
6.2 未來展望 80
參考文獻 82

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