隨著現今科技越趨進步，許多電子產品強調多功能、重量輕及體積小的訴求，使的產品中電晶體需要不段的微縮符合市場的需求，在微縮的過程中，會因為製程技術上的難度、遇到短通道效應，以及達到物理極限，這一連串的挑戰，是我們需要解決的。而使用通道、源極、汲極相同濃度，相同摻雜形態的無接面式電晶體，可以有效改善這些問題。而這種新穎的想法，除了可以改善這些問題，它也可以有效降低製程步驟，以及有較低的熱預算。
基於這個想法，此篇論文提出了混合式多層堆疊奈米薄片無接面式場效電晶體，搭配環繞式閘極作研究方向。混合式結構是藉由不同摻雜形態的特性讓它有效的通道厚度減少，而堆疊結構，我們利用分次成長多晶矽，再利用氧化薄化的方式達到我們所需要的厚度，相對於傳統式直接沉積所需要的厚度，它能有更大的晶粒與較少的晶界。最後再搭配環繞式閘極來增加閘極控制能力，以提升控制開關的能力，以及降低漏電流。
此篇論文開發的混合式堆疊無接面式場效電晶體，其通道有著三面式環繞的閘極以及奈米線(Nanowieres)。此元件展現了極佳的電特性以及可靠度，像是有較低的汲極引致能障(Drain-induced barrier lowering,DIBL)為7mV/V、較高的開關電流比(Ion/Ioff current ratio>107),以及不錯的陡峭之次臨界擺幅(Subthreshold swing ,SS )190 mV/dec，此外針對結構的I-V特性有作深入的探討，利用加熱的方式來看其特性變化，最後我再利用TCAD模擬軟體來配合實驗作特性分析。
提出此混合式多層堆疊無接面式場效電晶體搭配環繞式的閘極的研究，其有良好的電特性且製程上相當簡單，因此對於未來的發展，此結構能在3D結構上有效的利用或者配合消耗功率元件作使用。

With the advanced technology that many electrical device emphasize on multi-functional, lightweight, and small size, etc. As device scaling, it will face lots of manufacture’s technique problems such as short channel effect (SCE). The worst is the device may reach the physical limit. A series of challenge is what we need to solve. We set the device’s channel, source, drain doping type all the same. And device will be the junctionless field mosfet. JL FinFET can improve these problems. It also can effectively cut down the manufacture’s process, furthermore, it has lower thermal budget.
Based on this idea, this research proposes the multi-stacking hybrid nanosheet layers Junctionless Field-Effect transistor with surrounding poly gate. By using different doping type to reduce the effective channel thickness. On the other hand, we deposit poly-Si several times to get the multi-stacking structure. By use of oxide trimming to realize our channel thickness, while the traditional device directly deposit its thickness, it will get bigger grain size and lower grain boundary. Finally, the device with surrounding gate to elevate the control ability, and reduce the leakage.
This thesis develop the hybrid multi-stacking junctionless field effect transistor, it channel has surrounding gate and nano-sheet. The device has excellent electrical properties and reliabilities. For example, it has lower DIBL(Drain-induced barrier lowering ) 7mV/V, higher current ratio (> 107) and good subthreshold swing (SS 190mV/dec). Furthermore, we focus on I-V curve research, we use heat the device to get higher temperature for observing the characteristic varieties. Finally, I use TCAD simulation to cooperate with my device’s characteristics.
Propose the novel hybrid multi-stacking junctionless field-effect transistor, its good electrical and simple manufacture’s process may be the useful way to apply in future development. The device also has the better properties on low power consumption applications and three-dimensional stacked ICs applications.

Contents
中文摘要 ii
Abstract iv
Acknowledge vi
Contents vii
Figure Captions ix
Chapter 1 - 1 -
Introduction - 1 -
1-1. Challenge of Scaling Down the Device - 1 -
1-2. Introduction of accumulation and junctionless mode - 6 -
1-3. Parameters extraction for MOSFET - 9 -
A. Threshold voltage (Vth) - 9 -
B. Subthreshold swing (SS) - 9 -
C. ON/OFF current ratio(Ion/Ioff) - 10 -
D. Drain Induced Barrier Lowering(DIBL) - 10 -
E. Gate induced Drain Leakage(GIDL) - 11 -
1-4. Motivation - 13 -
1-4-1 Nature length - 13 -
1-4-2 Poly-silicon thin down - 14 -
1-4-3 Multi-stacking layer - 15 -
1-4-4 Hybrid Junctionless Transistors - 19 -
1-5. Dissertation Organization - 20 -
Chapter 2 - 21 -
Junctionless Mechanism - 21 -
2-1. Principle of Junctionless Transistor - 21 -
2-2. Short Channel Effects in Junctionless transistor - 29 -
2-3. Junctionless device versus Temperature - 31 -
2-4. Hot carrier reliability of Junctionless - 33 -
Chapter 3 - 35 -
Device Structure and Fabrication - 35 -
3-1. Device Fabrication Process: - 35 -
3-2. Images Analysis - 39 -
3-2-1 SEM image of the device structure - 39 -
3-2-2 TEM image of the device structure - 41 -
3-3. Device structure simulation - 43 -
Chapter 4 - 45 -
Device Electrical Analysis - 45 -
4-1. Multi-stacking hybrid structure and single channel device - 45 -
4-2. Temperature versus Device performance - 59 -
4-3. Device simulation and performance - 61 -
Chapter 5 - 66 -
Conclusion - 66 -
Reference - 67 -

Reference
Chapter 1
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Chapter 3
[3-1] B. Kim, S. H. Lim, D. W. Kim, T. Nakanishi, S. Yang, J. Y. Ahn, et al.,
"Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash,"
in 2011 International Reliability Physics Symposium, 2011, pp. 2E.4.1-2E.4.4.
[3-2] Y. C. Cheng, H. B. Chen, C. Y. Chang, C. H. Cheng, Y. J. Shih, and Y. C. Wu, "A
highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid
P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs," in 2016 IEEE
Symposium on VLSI Technology, 2016, pp. 1-2.
[3-3] T. C. Liao, S. W. Tu, M. H. Yu, W. K. Lin, C. C. Liu, K. J. Chang, et al., "Novel
Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels," IEEE Electron
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Chapter 4
[4-1] S. G. Chamberlain and S. Ramanan, "Drain-induced barrier-lowering analysis in
VSLI MOSFET devices using two-dimensional numerical simulations," IEEE
Transactions on Electron Devices, vol. 33, pp. 1745-1753, 1986.
[4-2] C. W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, et al.,
"High-Temperature Performance of Silicon Junctionless MOSFETs," IEEE
Transactions on Electron Devices, vol. 57, pp. 620-625, 2010.
[4-3] M. Cho, G. Hellings, A. Veloso, E. Simoen, P. Roussel, B. Kaczer, et al., "On and off
state hot carrier reliability in junctionless high-K MG gate-all-around nanowires," in
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[4-4] TCAD Sentaurus Device, Ver.G-2012.06, Synopsys 2012.
[4-5] Synopsys Sentaurus Device’s manual,2015

Chapter 5
[5-1] Y. C. Cheng, H. B. Chen, C. Y. Chang, C. H. Cheng, Y. J. Shih, and Y. C. Wu, "A
highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid
P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs," in 2016
IEEE Symposium on VLSI Technology, 2016, pp. 1-2.
[5-2] B. Kim, S. H. Lim, D. W. Kim, T. Nakanishi, S. Yang, J. Y. Ahn, et al., "Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash," in 2011 International Reliability Physics Symposium, 2011, pp. 2E.4.1-2E.4.4.
[5-3] C. W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, et al., "High-Temperature Performance of Silicon Junctionless MOSFETs," IEEE Transactions on Electron Devices, vol. 57, pp. 620-625, 2010.