隨著製程技術日益進步，如何提升快閃記憶體操作特性又能提高元件密度為重要的課題，目前有許多方法被提出，使用堆疊式電荷儲存層就是一種有效的方式。本篇論文在環繞閘極無接面快閃記憶體元件上，將含較高電荷陷阱密度的富鋯金屬氧化層、氨電漿處理的氧化鋯有較深陷阱能階、有較高介電常數的AlN材料應用於堆疊電荷捕捉層中，透過改變電荷陷阱密度的多寡、陷阱能階、介電常數等，來影響元件操作特性。
　　本論文分為三個部分，第一部分比較了Si3N4/ZrO2控制片、加入富鋯金屬氧化層於high-k電荷捕捉層中的底部、中央、頂部樣品，探討其對元件操作特性的影響。從實驗結果得知，在high-k電荷捕捉層底部加入富鋯金屬氧化層，因其含氧空缺、且能隙較小的特性，使得high-k層中的電荷分布較靠近前段，提升了元件的寫入及抹除速度，然而卻也因此導致了較差的電荷保持力。
　　第二部分探討不同氮化程度的堆疊電荷儲存層對元件特性的影響。從實驗結果得知，使用ZrON/ZrO2堆疊及ZrON作為high-k電荷捕捉層的元件，因為經過較多的氨電漿處理，降低了介電層中的淺缺陷數量，所以有較慢的寫入及抹除速度，然而由於淺缺陷數量較少，且氨電漿處理也鈍化了薄膜中的漏電流路徑，使元件有較好的電荷保持力。
　　第三部分，將AlN材料應用於堆疊電荷儲存層中，與Si3N4/ZrO2控制片做比較。實驗結果顯示使用AlN作為前端電荷捕捉層的元件，有較快的寫入抹除速度，因AlN的介電常數較Si3N4高，在寫入抹除操作時能有較大的穿隧電場。電荷保持力方面，AlN作為前端電荷捕捉層，表現沒有Si3N4來的好，另外從實驗結果發現，若在AlN及ZrO2中間插入一層Al2O3做為能障，會使ZrO2中的電荷較難脫離，有助於電荷保持力的表現。寫入抹除耐久力方面，若使用AlN作為前端電荷儲存層，元件會有越來越難寫入的趨勢。Si3N4與ZrO2堆疊的元件有不錯的寫入抹除耐久力，在經過多次寫入抹除後，記憶窗並沒有太大的改變。

　　With the advancement of manufacturing technology, improvement of the device operation characteristics and device density become the important issues. Some approaches have been proposed. Stacked trapping layer was reported as an effective way. In this thesis, Zr-rich ZrO2, NH3 plasma treatment, and AlN material were applied in stacked charge trapping layer of Gate-All-Around Junctionless device. The devices operation characteristics were influenced by charge trap density, trap energy level, and dielectric constant, etc.
　　The thesis includes three parts as follows. In the first part, the Zr-rich ZrO2 was placed at the different location of high-k trapping layers and the effect upon the operating characteristics is studied. In this work, the programing and erasing speeds can be enhanced by applying Zr-rich ZrO2 at the bottom of high-k trapping layer. This enhancement can be attributed to the distribution of trapped charge which was closer to the bottom side of high-k trapping layer. However, the device with Zr-rich ZrO2 at the bottom of high-k trapping layer shows worse retention characteristic for the same reason.
　　In the second part, effects of NH3 plasma treatment on stacked charge trapping layer were investigated. The devices with ZrON/ZrO2 and ZrON high-k trapping layer show both slower programing and erasing speeds. This can be attributed to less amount of shallow trap in high-k trapping layer by applying NH3 plasma treatment. However, both ZrON/ZrO2 and ZrON devices show better retention characteristic. This improvement can be attributed to the fact that the leakage paths which were passivated by nitrogen and hydrogen.
　　In the third part, AlN material was applied in stacked charge trapping layer. From the experiment results, the devices with AlN as front charge trapping layer show faster programing and erasing speeds. Because the dielectric constant of AlN is higher than Si3N4, the electric field across tunneling layer are higher during programing and erasing operation. In terms of retention characteristic, the devices with AlN as front charge trapping layer show worse retention characteristic than the devices with Si3N4 as first charge trapping layer. Furthermore, by inserting an Al2O3 and ZrO2 trapping layer, the retention characteristic can be improved duo to additional energy barrier which may effectively block the trapped charge in ZrO2 from escaping. In terms of endurance characteristic, the devices with AlN as front charge trapping layer show slower programing speed with increasing PE cycles. Memory window of the device with Si3N4/ZrO2 stacked charge trapping layer shows no significant difference after PE cycles.

摘要 i
Abstract iii
致謝 v
目錄 vi
圖目錄 ix
表目錄 xii
第一章 序論 1
1.1 快閃記憶體元件 1
1.1.1 浮動閘極式快閃記憶體元件 1
1.1.2 電荷捕捉式快閃記憶體元件 2
1.2 多晶矽薄膜電晶體 4
1.3 多向式閘極結構與奈米線通道式快閃記憶體元件 4
1.4 介電係數材料與能帶工程 6
1.4.1 高介電系數材料 6
1.4.2 能帶工程 7
1.5 無接面快閃記憶體元件介紹 8
第二章 快閃記憶體元件製程與操作方法 16
2.1 快閃記憶體元件製程 16
2.1.1 環繞式閘極無接面通道元件 16
2.2 快閃記憶體元件寫入與抹除方法 17
2.2.1 CHEI通道熱電子注入寫入 17
2.2.2 F-N穿隧寫入 18
2.2.3 F-N穿隧抹除 19
2.3 快閃記憶體元件可靠度特性 20
2.3.1 電荷保持力 20
2.3.2 耐久力 21
2.3.3 閘極與汲極之干擾特性 22
2.4 快閃記憶體元件量測方法 23
2.4.1 F-N穿隧寫入與抹除量測 23
2.4.2 電荷保持力量測 23
2.4.3 耐久力量測 24
第三章 氮化矽/二氧化鋯堆疊電荷儲存層加入富鋯金屬氧化層對多晶矽環繞閘極快閃記憶體元件特性研究 33
3.1 研究動機與背景 33
3.2 實驗流程 34
3.3 實驗結果與討論 35
3.3.1 元件汲極電流對閘極電壓特性圖 35
3.3.2 元件寫入與抹除特性 36
3.3.3 元件可靠度特性 37
3.4 結論 37
第四章 氨電漿氮化氮化矽/二氧化鋯堆疊電荷儲存層對多晶矽環繞閘極快閃記憶體元件特性研究 46
4.1 研究動機與背景 47
4.2 實驗流程 47
4.3 實驗結果與討論 49
4.3.1 元件汲極電流對閘極電壓特性圖 49
4.3.2 元件寫入與抹除特性 49
4.3.3 元件可靠度特性 50
4.4 結論 51
第五章 AlN/High-k堆疊電荷儲存層多晶矽環繞閘極快閃記憶體之特性探討 58
5.1 研究動機與背景 59
5.2 實驗流程 60
5.3 實驗結果與討論 61
5.3.1 元件汲極電流對閘極電壓特性圖 61
5.3.2 元件寫入與抹除特性 61
5.3.3 元件可靠度特性 62
5.4 結論 63
第六章 結論與未來展望 73
6.1 結論 73
6.2 未來展望 75
參考文獻 76

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