本篇碩士論文，運用TCAD半導體輔助模擬程式研究了結構為P-I-M的穿隧電晶體。藉由新型穿隧電晶體汲極端的金屬，取代了傳統穿隧電晶體汲極端的矽原子，能有效地提高電流開關特性並且簡化製程難易度。根據模擬結果顯示，新型穿隧電晶體P-I-M汲極端選用功函數值為4.25 eV的金屬相對於傳統的穿隧電晶體P-I-N，在元件關閉狀態下，不論大小汲極偏壓，皆能有效地抑制雙極效應，降低漏電流的損耗，在大汲極偏壓下，P-I-M結構增加了載子漏電流的穿隧能障厚度；小汲極偏壓下，P-I-M結構降低了載子的複合率，此外，導通電流對於這兩個結構沒有太大的差異，新結構的漏電流下降了276倍，並提升了兩個數量級的元件導通-關閉電流比值，也降低次臨限擺幅。最重要的是，新型結構P-I-M在實際製程上是容易的，汲極端金屬存在著例如TaSix 與TixSi1-x等矽化物，且金屬功函數存在著0.15 eV的範圍選擇空間，在範圍內P-I-M結構的穿隧電晶體比P-I-N結構擁有更多優勢。

In this paper, a P-I-M TFET is proposed and investigated by TCAD simulator. Using a new n-TFET structure that replaces traditional semiconductor material at drain with metal was proposed to enhance device performance while simplifying process. By employing metal with an appropriate work function (WF) of 4.25 eV, based on simulation results, the proposed P-I-M TFET is superior to traditional P-I-N structure by exhibiting suppressed ambipolar effect for both low and high drain bias due respectively to wider tunneling barrier and lower Shockley-Read-Hall (SRH) recombination rate at off state. In addition, improved off-state current by a factor of 276, enhanced on-state and off-state current ratio (ION/IOFF) by 2 orders and improved subthreshold swing (SS) with comparable on-state drive current are achieved. More importantly, the idea of P-I-M structure is feasible from the viewpoint of process integration since metal with such WF is a fab-friendly material such as TaSix and TixSi1-x, and the variation of metal WF up to 0.15 eV is also allowed to keep the advantage of IOFF over P-I-N TFET. The P-I-M TFET is very to implement green electronics with higher performance at lower cost.

目錄
摘要……………………………………………………………………………………i
Abstract………………………………………………………………………………..ii
誌謝…………………………………………………………………………………...iii
目錄…………………………………………………………………………………...iv
圖目錄……………………………………………………………………………….. vi


第一章 緒論………………………………………………………………………..1
1-1 研究背景……………………………………………………………………...1
1-2 穿隧式場效電晶體的介紹…………………………………………………….2
1-3 穿隧式場效電晶體的操作機制……………………………………………….2
1-4 穿隧式場效電晶體面臨的挑戰……………………………………………….3
1-5 雙極性效應…………………………………………………………………….4
1-6 研究動機……………………………………………………………………….4
1-7 論文結構……………………………………………………………………….4





第二章 文獻回顧…………………………………………………………………11
2-1 提升導通電流的方法………………………………………………………...11
2-2 改善雙極性效應的方法……………………………………………………...12
2-3 穿隧式場效電晶體電流組成分析…………………………………………...13

第三章 實驗結果與討論…………………………………………………………21
3-1 模擬結構……………………………………………………………………...21
3-2 汲極端施加金屬的差別……………………………………………………...22
3-3 汲極端不同金屬功函數的比較……………………………………………...23
3-4 金屬汲極與通道間距的選擇………………………………………………...25

第四章 結論與未來展望…………………………………………………………37

參考文獻………………………………………………………………..…………39












圖目錄
第一章
圖1-1電晶體下一世代具有潛力的方向………………………….…………….…6
圖1-2元件的微縮與Vdd、Vth的關係圖……………………………………….….6
圖1-3元件的微縮與元件功率、漏電流功率損耗的關係圖………………….….7
圖1-4 MOSFET與TFET的電性比較關係圖…………………………………... .7
圖1-5 N-type與P-type穿隧電晶體操作原理示意圖……………………….……8
圖1-6 TFET與MOSFET的電性比較圖………………………………………….8
圖1-7雙極性效應電性示意圖………………………………………………….....9
圖1-8雙極性效應現象能帶示意圖……………………………………………….9
圖1-9雙極性效應電性示意圖…………………………………………………...10
圖1-10 改善雙極性效應方法示意圖……………………………………………10

第二章
圖2-1 同質接面與異質接面對電子穿隧機率差別示意圖……………………..14
圖2-2 P型穿隧電晶體Source與Channel間加入一層p+結構示意圖………..14
圖2-3 結構施加p+層能帶差異示意圖………………………….………………15
圖2-4 N型穿隧電晶體在Source與Channel間加入一層n+摻雜示意圖……..15
圖2-5 結構摻雜n+層能帶關係差異示意圖…………………………………….16
圖2-6 結構摻雜n+層電性比較示意圖………………………………………….16
v
圖2-7 電晶體預留Lgap結構示意圖……………………………………………...17
圖2-8 結構預留Lgap區域的能帶差異示意圖…………...……………………....17
圖2-9 正常濃度與低濃度摻雜的能帶關係示意圖……………………………..18
圖2-10 不同汲極濃度摻雜的電性比較圖………………………………………18
圖2-11 Channel與Drain之間選用寬能隙材料結構示意圖…………………...19
圖2-12 Channel與Drain之間選用寬能隙材料能帶關係示意圖……………...19
圖2-13 穿隧電晶體的電流分析…………………………………………………20

第三章
圖3-1傳統鰭式穿隧電晶體結構圖……………………..………………………..27
圖3-2改良鰭式穿隧電晶體結構圖……………………..………………………..27
圖3-3汲極偏壓為0.05 V與1 V時，結構P-I-N與結構P-I-M的電性比較圖…28
圖3-4結構 P-I-N與結構P-I-M在元件關閉，汲極偏壓為1 V的能帶關係圖…28
圖3-5結構P-I-N結構複合率分佈圖…………….…………..…………………..29
圖3-6結構P-I-M結構複合率分佈圖………………………..………………….29
圖3-7結構P-I-N與結構P-I-M的S.S._Id關係圖……………………………….30
圖3-8不同金屬功函數，從4.1 eV到4.5 eV，在Vd=0.05 V時的電性比較圖…30
圖3-9金屬功函數為4.1 eV與4.25 eV的能帶關係比較圖…….………………..31
圖3-10金屬功函數為4.25 eV與4.5 eV的能帶關係比較圖……..……………31
圖3-11 Vd=0.05 V 時，漏電流與金屬功函數的關係圖…………………………32
圖3-12 Vd=1 V 時，漏電流與金屬功函數的關係圖…………………………….32
圖3-13 P-I-M結構圖……………………………………………………………...33
圖3-14 汲極偏壓為0.05 V時，不同Lgap長度，10、15、25 nm對結構P-I-N穿隧電晶體的電性圖………………………………………………………33
圖3-15汲極偏壓為1 V時，不同Lgap長度，10、15、25 nm對結構P-I-N穿電晶體的電性圖……………………………………………………………34
圖3-16 汲極偏壓為0.05 V時，不同Lgap長度，10、15、25 nm對結構P-I-M穿隧電晶體的電性圖……………………………………………………34
圖3-17 汲極偏壓為1 V時，不同Lgap長度，10、15、25 nm對結構P-I-M穿隧電晶體的電性圖………………………………………………………35
圖3-18 Lgap =10 nm時，結構P-I-N與結構P-I-M的電性比較…………….…..35
圖3-19 Lgap =15 nm時，結構P-I-N與結構P-I-M的電性比較…………….…..36
圖3-19 Lgap =25 nm時，結構P-I-N與結構P-I-M的電性比較…………….…..36

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