現今電子產品持續追求低耗電、低成本以及輕薄短小……等趨勢，而在微縮過程中面臨到的短通道效應以及物理極限對一般傳統電晶體是個挑戰，然而無接面電晶體的誕生減輕了以上的問題。無接面電晶體的特色就是其源極、汲極以及通道摻雜的型態、濃度皆一致，也因為沒有接面存在於通道與源極、汲極之間，故稱無接面電晶體。此電晶體不僅可降低製程熱預算、抑制短通道效應，還有反應速度更快、消耗功率更低…等優點，是將來值得注意的新穎元件之一。
在本篇論文中，提出了殼狀混合式多晶矽無接面場效電晶體搭配N型成長摻雜 (In-situ doping) 於P 型基板上之研究。我們藉由調整曝光劑量的方式，降低製程步驟與時間，用同一道光罩就可以完成N型通道、P型基板的蝕刻，另外實驗組以及對照組也是採用以上同一道光罩。採用混合式結構是藉由 N 型通道與P 型基板在垂直方向上產生空乏區並造成等效通道厚度減少，通道厚度減少可增強閘極對通道的控制能力，另外我們也採用了三閘極 (Tri-gate) 的結構來提升元件的開關能力用以減少漏電流並減少耗能。
本篇論文開發的殼狀混合式多晶矽無接面場效電晶體，此元件展現優越的電特性，譬如陡峭的次臨界擺幅 (Subthreshold swing, S.S.) 為 95mV/dec.、開關電流特性 (Ion/Ioff current ratio > 5×106) 以及較低的汲極導致能障下降值 (Drain induced barrier lowering, DIBL) 為 50 mV/V，另外也討論了此元件在高溫下的電特性。最後一部分我們進行模擬分析，使用Sentaurus TCAD 模擬軟體與實驗數據作比較。
此殼狀混合式多晶矽無接面場效電晶體有良好的電特性且製程上也相當簡易，因此非常有潛力應用在將來的低消耗功率元件以及三維的堆疊結構上。

Nowadays, electronic products tend to the trend of low power consumption, low cost and small size. Because of the products miniaturization, the short-channel effects and physical limitations will be a challenge for conventional transistors. However, the birth of junctionless transistors has been reduced above problems probably. The characteristics of the junctionless transistor is that the source, drain and the channel doping have all the same type and concentration, and because no junction exists between the channel and S/D, the junctionless transistor is called. Junctionless transistor not only reduces the thermal budget of the process, but also suppresses the short-channel effects. It is one of the novel structure worth noting in the future.
This work proposes the N+/P hybrid poly-Si shell structure junctionless field-effect transistors with N+ in-situ doping on the p-type substrate. We adjusted the exposure dose to reduce the process flow and time, and we used the same mask to complete the N-channel and P-type substrate etching step. In order to turn-off the JL-FET architecture, the multi-gate structure and ultra-thin body (UTB) are the candidate to achieve the full depletion region at off-state. It can improve the switching capability of the device to reduce leakage current and power consumption. Since the depletion region formed between N+ channel and p-type substrate interface, it is used to reduce channel thickness (Tch) and turn off the device more easily.
This work exhibits the N+/P hybrid poly-Si shell structure junctionless field-effect transistors. The NW shell JL-FET exhibits the superior electrical properties, including high ON/OFF current ratio (>5×106), steep subthreshold swing (95 mV/dec.) and low value of Drain Induced Barrier Lowering (50 mV/V). We also discuss the electrical characteristics of this device at high temperatures. In the last part, we use Sentaurus TCAD simulation software to analyze this device, and compare the simulation results with the experimental data.
The N+/P hybrid poly-Si shell structure junctionless field-effect transistors has excellent electrical characteristics and is simple to process, so it has tremendous potential application on low-power devices and three-dimensional stack structures in the future.

中 文 摘 要 i
Abstract iii
Acknowledge v
Contents vi
Figure Captions viii
Chapter 1 - 1 -
Introduction - 1 -
1-1 Challenge of Moore’s law - 1 -
1-2 Introduction of Junctionless transistor - 4 -
1-3 Motivation - 9 -
1-4 Dissertation Organization - 16 -
Chapter 2 - 17 -
Junctionless Transistor Mechanism - 17 -
2-1 Advantage of Junctionless Transistor - 17 -
2-2 Basic Principle of Junctionless Transistor - 21 -
2-3 Short Channel Effects (SCE) in Junctionless Transistors - 28 -
Chapter 3 - 31 -
Device Fabrication and Structure - 31 -
3-1 Device Fabrication Process - 31 -
3-1-1 Fabrication flow - 31 -
3-1-2 Mask Free Electron Beam Lithography Method - 35 -
3-2 Device Images Analysis - 39 -
3-2-1 SEM (Scanning Electron Microscope) image of device structure - 39 -
3-2-2 SIMS profile of device structure - 41 -
3-2-3 TEM image of device structure - 43 -
Chapter 4 - 46 -
Electrical Characteristics Analysis - 46 -
4-1 Device Electrical Analysis - 46 -
4-2 Device Temperature Performance - 55 -
4-3 Device Simulation - 58 -
Chapter 5 - 62 -
Conclusion - 62 -
Reference - 63 -

Chapter 1
[1-1] G. E. Moore, “Cramming more components onto integrated circuits”, Proceedings of the IEEE, vol. 86, pp. 82-85, 1965.
[1-2] Zsolt Tőkei IMEC, “Sub-5nm Interconnect Trends and Opportunities”, 2017 IEEE International Electron Devices Meeting, San Francisco, 2017, pp. 161.
[1-3] C. W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, et al., "High-Temperature Performance of Silicon Junctionless MOSFETs," IEEE Transactions on Electron Devices, vol. 57, pp. 620-625, 2010.
[1-4] C.-W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, et al., "Performance estimation of junctionless multigate transistors," Solid-State Electronics, vol. 54, pp. 97-103, 2010/02/01/ 2010.
[1-5] H. C. Lin, C. I. Lin, Z. M. Lin, B. S. Shie, and T. Y. Huang, "Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness," IEEE Transactions on Electron Devices, vol. 60, pp. 1142-1148, 2013.
[1-6] Y. C. Cheng, H. B. Chen, C. S. Shao, J. J. Su, Y. C. Wu, C. Y. Chang, et al., "Performance enhancement of a novel P-type junctionless transistor using a hybrid poly-Si fin channel," in 2014 IEEE International Electron Devices Meeting, 2014, pp. 26.7.1-26.7.4.
[1-7] M. H. Han, C. Y. Chang, H. B. Chen, J. J. Wu, Y. C. Cheng, and Y. C. Wu, "Performance Comparison Between Bulk and SOI Junctionless Transistors," IEEE Electron Device Letters, vol. 34, pp. 169-171, 2013.
[1-8] J. P. Colinge, A. Kranti, R. Yan, C. W. Lee, I. Ferain, R. Yu, et al., "Junctionless Nanowire Transistor (JNT): Properties and design guidelines," Solid-State Electronics, vol. 65-66, pp. 33-37, 2011/11/01/ 2011.

Chapter 2
[2-1] M. Cho, G. Hellings, A. Veloso, E. Simoen, P. Roussel, B. Kaczer, et al., "On and off state hot carrier reliability in junctionless high-K MG gate-all-around nanowires," in 2015 IEEE International Electron Devices Meeting (IEDM), 2015, pp. 14.5.1-14.5.4.
[2-2] H. Yang, Y. Guo, Y. Hong, J. Yao, J. Zhang, and X. Ji, "P-n channel junctionless transistor," in 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014, pp. 1-3.
[2-3] C. W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, et al., "High-Temperature Performance of Silicon Junctionless MOSFETs," IEEE Transactions on Electron Devices, vol. 57, pp. 620-625, 2010.
[2-4] J. P. Colinge, C. Lee, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti, and R. Yu, Junctionless Transistors: Physics and Properties, Semiconductor-On-Insulator Materials for Nanoelectronics Applications, New York, USA, Springer-Verlag, 2011, Chapter 10, pp. 187–200.
[2-5] C.-W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, et al., "Performance estimation of junctionless multigate transistors," Solid-State Electronics, vol. 54, pp. 97-103, 2010/02/01/ 2010.
[2-6] C. W Lee, I. Ferain, A. Kranti, N. Dehdashti Akhavan, P. Razavi, R. Yan, et al., "Short-Channel Junctionless Nanowire Transistors", 2010.
[2-7] P. Kumar, S. Singh, N. P. Singh, B. Modi, and N. Gupta, "Germanium v/s silicon Gate-all-around junctionless nanowire transistor," in 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS), 2014, pp. 1-5.

Chapter 3
[3-1] Mohammad Ali Mohammad, Mustafa Muhammad, Steven K. Dew, and Maria Stepanova, Nanofabrication: Techniques and Principles, Springer-Verlag Wien, 2012, chapter 2, pp.11– 41.

Chapter 4
[4-1] C. W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, et al., "High-Temperature Performance of Silicon Junctionless MOSFETs," IEEE Transactions on Electron Devices, vol. 57, pp. 620-625, 2010.
[4-2] Y.-C. Cheng, H.-B. Chen, M.-H. Han, N.-H. Lu, J.-J. Su, C.-S. Shao, et al., "Temperature dependence of electronic behaviors in quantum dimension junctionless thin-film transistor," Nanoscale Research Letters, vol. 9, p. 392, 2014/08/13 2014.
[4-3] Y. C. Cheng, H. B. Chen, C. S. Shao, J. J. Su, Y. C. Wu, C. Y. Chang, et al., "Performance enhancement of a novel P-type junctionless transistor using a hybrid poly-Si fin channel," in 2014 IEEE International Electron Devices Meeting, 2014, pp. 26.7.1-26.7.4.
[4-4] Y. C. Cheng, H. B. Chen, C. Y. Chang, C. H. Cheng, Y. J. Shih, and Y. C. Wu, "A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs," in 2016 IEEE Symposium on VLSI Technology, 2016, pp. 1-2.