|
[1] S.-H. Wang, "An ecient algorithm for rule-based layout pattern matching," Master Thesis, National Tsing Hua University, 2017. [2] P. Gupta, A. B. Kahng, S. Nakagawa, S. Shah, and P. Sharma, "Lithography simulation- based full-chip design analyses," in Proceedings of Society of Photographic Instrumentation Engineers, vol. 6156, 2006. Art. ID 61560T. [3] A. B. Kahng, C.-H. Park, and X. Xu, "Fast dual graph based hotspot detection," in Proceed- ings of Society of Photographic Instrumentation Engineers, vol. 6349, pp. 628{635, 2006. [4] H. Yao, S. Sinha, C. Chiang, X. Hong, and Y. Cai, "Ecient process hotspot detection using range pattern matching," in Proceedings of International Conference on Computer Aided Design, pp. 625{632, 2006. [5] D. Ding, J. Torres, A, G. Pikus, F, and Z. Pan, D, "High performance lithographic hotspot detection using hierarchically rened machine learning," in Proceedings of Asia and South Pacic Design Automation Conference, pp. 775{780, 2011. [6] J.-Y. Wuu, F. G. Pikus, A. Torres, and M. Marek-Sadowska, "Rapid layout pattern classica- tion," in Proceedings of Asia and South Pacic Design Automation Conference, pp. 781{786, 2011. [7] W.-Y. Wen, J.-C. Li, S.-Y. Lin, J.-Y. Chen, and S.-C. Chang, "A fuzzy-matching model with grid reduction for lithography hotspot detection," IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems, vol. 33, no. 11, pp. 1671{1680, 2014. [8] Y.-T. Yu, G.-H. Lin, I. H.-R. Jiang, and C. Chiang, "Machine-learning-based hotspot de- tection using topological classication and critical feature extraction," IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems, vol. 34, no. 3, pp. 460{470, 2015. [9] J.-Y. Wuu, F. G. Pikus, A. Torres, and M. Marek-Saowska, "Detecting context sensitive hotspots in standard cell libraries," in Proceedings of Society of Photographic Instrumentation Engineers, vol. 7275, p. 727515, 2009. [10] Y.-T. Yu, Y.-C. Chan, S. Sinha, I. H.-R. Jiang, and C. Chiang, "Accurate process-hotspot detection using critical design rule extraction," in Proceedings Design Automation Conference, pp. 1163{1168, 2012. [11] J. W. Park, R. Todd, and X. Song, "Geometric pattern match using edge driven dissected rectangles and vector space," IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems, vol. 35, no. 12, pp. 2046{2055, 2016. [12] F. Pikus, "Topological pattern matching," U.S. Patent 018 594 A1, 2010. [13] F. Gennari, "Fast pattern matching," U.S. Patent 7 818 707, 2010. [14] "Introduction to parallel computing." https://computing.llnl.gov/tutorials/ parallel_comp/. [15] "Openmp - the openmp api specication for parallel programming." http://www.openmp. org/. [16] "POSIX Threads Programming." https://computing.llnl.gov/tutorials/pthreads/. [17] R. O. Topaloglus, "ICCAD-2016 Contest - Pattern classication for integrated circuit design space analysis," http://cad-contest-2016.el.cycu.edu.tw/Problem_C/default.html/. [18] H.-Y. Su, C.-C. Chen, Y.-L. Li, A.-C. Tu, C.-J. Wu, and C.-M. Huang, "A novel fast lay- out encoding method for exact multilayer pattern matching with prufer encoding," IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems, vol. 34, no. 1, pp. 95{108, 2015. 30 |