毫米波頻帶擁有大量的可用頻寬，因此相當適合使用於下一世代的行動通訊系統。而為了避免毫米波短波長引起的嚴重信號衰減和路徑損耗，多輸入多輸出毫米波系統利用大量傳送、接收天線陣列以減少訊號衰減。然而大量的天線導致所需的射頻鏈和數位類比轉換器較多，導致成本與功耗也較大。因此有了類比數位混合式預編碼架構來減少所需的射頻鏈、數位類比轉換器。混合預編碼器將預編碼過程分為部分在類比端作、部分在數位端作，來減少預編碼過程中減少數位類比間所需的取樣數。本論文提出了一種基於平行資料流架構的可擴展式低複雜度混合預編碼演法，使每筆資料流獨立作計算。本論文所提出的預編碼演算法使用TSMC 40nm CMOS製程來實作成硬體。所提出的預編碼處理器使用於16x16多輸入多輸出系統，且支援最多4筆資料流。處理器的最高頻率為120MHz，功耗為139mW。且處理器在1/2/3/4個資料流可分別達到6.67M/6.67M/6.67M/6.67M通道矩陣/每秒的吞吐量。

Millimeter wave (mmWave) multiple-input and multiple-output (MIMO) system provides high throughput for next generation system. To avoid severe signal attenuation and path loss caused by short wavelength, mmWave MIMO system utilizes large antenna arrays in transmitter and receiver to reduce fading. However, the high cost of radio frequency (RF) chain and data converter limits the number of antennas. Thus, hybrid analog/digital precoding was proposed to reduce the required number of RF chains and data converters under the condition of large antenna arrays. Hybrid precoding MIMO system divides precoding process into analog domain and digital domain in order to reduce the sampled data from digital precoding process.
In this thesis, we propose a scalable low complexity hybrid precoding algorithm based on parallel data-stream hardware architecture which enables independently computing for each data stream. Moreover, the proposed scalable precoding algorithm is implemented using TSMC 40 nm CMOS process technology. The proposed precoding processor supports the transmissions of 1 to 4 data streams for 16x16 mmWave MIMO systems. The operating frequency of this chip is 120 MHz and power consumption is 139 mW. The normalized throughput of this chip achieves 6.67M/6.67M/6.67M/6.67M channel-matrices per second in 1/2/3/4 data streams.

1 Introduction 1
1.1 Millimeter Wave MIMO Systems . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Research Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Organization of This Thesis . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Hybrid Precoding for Millimeter Wave MIMO Systems 5
2.1 SVD-Based Digital Precoding . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Hybrid Analog/Digital Precoding . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1 Fully-connected Architecture . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 Sub-connected Architecture . . . . . . . . . . . . . . . . . . . . . 12
2.2.3 Fully-connected Bitstream-based Architecture . . . . . . . . . . . 14
2.3 Channel Model for Millimeter Wave MIMO Systems . . . . . . . . . . . . 15
2.4 Hybrid Precoding/Combining Algorithms . . . . . . . . . . . . . . . . . . 17
2.4.1 Simultaneous Orthogonal Matching Pursuit (SOMP) . . . . . . . 17
2.4.2 Parallel-Index-Selection Matrix-Inverse-Bypass Simultaneous Orthogonal Matching Pursuit (PIS-MIB-SOMP) . . . . . . . . . . . 19
2.4.3 Multiple Orthogonal Codebook with Local Search . . . . . . . . . 21
2.4.4 Greedy Hybrid Precoding (GHP) . . . . . . . . . . . . . . . . . . 24
2.4.5 SIC-based Hybrid Precoding . . . . . . . . . . . . . . . . . . . . . 25

3 Proposed Hybrid Precoding Algorithm 31
3.1 Bitstream-Based Greedy Hybrid Precoding . . . . . . . . . . . . . . . . . 31
3.2 Simulation Result and Computation Complexity . . . . . . . . . . . . . . 35

4 Hardware Architecture 43
4.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2 Hybrid Vector/Rotation Mode CORDIC Processor . . . . . . . . . . . . 45
4.3 Pipelined Summation/Multiplication/Subtraction Unit . . . . . . . . . . 46
4.4 Timing Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5 Implementation Result 51
5.1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.2 Layout Hierarchy and CHIP I/O . . . . . . . . . . . . . . . . . . . . . . 52
5.3 Chip Specification and Simulation . . . . . . . . . . . . . . . . . . . . . . 53

6 Conclusion 63

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