多使用者多輸入多輸出（MU-MIMO）系統是無線通訊系統中的一個熱門的題目。在傳統的MIMO通訊系統中，若有多使用者在系統內，只在時間上或頻率上作多工來給予使用者數據。然而，若是在空間上作多工，則可以提高速度與頻譜效率。通過精心設計的基於洩漏的預編碼器，我們能夠抑制使用者間的同頻干擾（CCI）並保持低的錯誤率。廣義特徵值分解（GEVD）是基於洩漏的預編碼方案中不可避免的運算，GEVD的複雜性也在此方案中占主要的複雜度。因此，我們需要設計低複雜度的GEVD硬體演算法。本文提出了一種無矩陣乘法的硬體演算法，並且只由加法器和移位器組成的坐標旋轉數字計算方法處理器（CORDIC）。本文詳細介紹了傳統和所提出的GEVD的算法，稱為CORDIC GEVD，並且實作CORDIC GEVD。在本文的最後，有實作的合成結果並與其他論文的演算法實作合成結果比較。

Multi-user multiple-input multiple-output (MU-MIMO) system is a popular issue in wireless communication system. It increases speed and spectral efficiency by sending data to different users at the same time within same bandwidth. By well-designed leakage-based precoding scheme, we are able to suppress co-channel interference (CCI) to remain good bit-error-rate performance. Generalized eigenvalue decomposition (GEVD) is an inevitable operation in leakage-based precoding scheme, and the complexity of GEVD also dominates under this scheme. As a result, designing a low complexity GEVD hardware algorithm is necessary.
This thesis proposed a matrix-multiplication-free hardware algorithm, and the hardware implementation is only composed of COordinate Rotation DIgital Computer (CORDIC) processors which is only composed of adders and shifters. The traditional algorithm and the proposed algorithm for calculating GEVD are introduced in detail in following content. There are some parameters in hardware implementation, and the simulations for deciding these parameters are also presented. In the end of this thesis, the synthesis result of this hardware implementation is also presented and compared this work to other works.

1 Introduction 1
1.1 Multi-User MIMO System (MU-MIMO System) . . . . . . . . . . . . . . 1
1.2 Research Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Organization of This Thesis . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Multi-user MIMO System and Precoding Scheme 5
2.1 Multi-user MIMO System Model . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Leakage-Based Precoding Scheme . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Generalized Eigenvalue Decomposition . . . . . . . . . . . . . . . . . . . 8
2.3.1 Definition of GEVD . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.2 Implementation of GEVD . . . . . . . . . . . . . . . . . . . . . . 10
3 Proposed CORDIC GEVD based on Block SVD Power Method 17
3.1 Block SVD Power Method . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Modified Block SVD Power Method . . . . . . . . . . . . . . . . . . . . . 19
3.3 CORDIC-Based Multiplication and Inverse Square Root . . . . . . . . . 20
3.4 CORDIC GEVD Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 26
4 Architecture Design 31
4.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 Decision of Implementation Parameters . . . . . . . . . . . . . . . . . . . 48
4.3 Precoding Processor Architecture . . . . . . . . . . . . . . . . . . . . . . 50
4.3.1 Memory-based Architecture . . . . . . . . . . . . . . . . . . . . . 51
4.3.2 Register-file-based Architecture . . . . . . . . . . . . . . . . . . . 59
4.4 Fixed-point Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.5 Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5 Conclusion 69

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