鐵電（FE）隨機存取存儲器（FRAM）微縮的主要挑戰是：在三維鐵電電容的垂直側壁上，保持高極化密度。由於HfOx的鐵電材料解決了CMOS的製程兼容性問題，因此這種新材料可以成為破壞性創新，取代鋯鈦酸鉛（PZT）的典型鐵電材料。研究者下一個問題將是：如何驗證HfOx 鐵電材料運用在130 nm技術節點？（先進的PZT晶片基於130 nm技術。） 通過流暢的晶體轉換假設和第一原理模擬，拉伸應變環境和TiN-（220）界面晶相，這兩個變因有助於增加FE晶相在HfOx材料中的體積百分比。因此，提出了兩種有效的方法來緩解HfZrOx晶體的甦醒效應：應力工程和優化的界面取向。我們提出了CMOS兼容的HfZrOx FRAM技術，該技術顯示出無甦醒特性，1010/109次的可靠度操作，在105°C / 85°C時推估的10年記憶特性，以及初始Pr = 25/18 (μC/ cm2)，分別在二維/三維鐵電元件上展示。除了鐵電元件性能之外，還討論了可靠的元件電容設計，給1T1C晶片的記憶保留測試波型，以及最大操作次數/可微縮性的評估算法。最後，基於FRAM性能，2T2C內存架構和最小的可感應電荷，AR為30的3D-FRAM技術可以維縮到”圓柱結構下的20 nm技術節點”。

The main challenge in ferroelectric (FE) random access memory (FRAM) scaling is maintaining a high polarization density on the vertical sidewall of three-dimensional (3D) FE capacitors. Because the HfOx-based FE technology solves the process compatibility problem with CMOS, the new material has become the game changer, replacing typical FE materials of lead zirconate titanate (PZT). The next question is how to scale the HfOx FE materials through the 130 nm technology node. (The advanced PZT chip is based on 130 nm technology). Through the fluent transition and first-principle simulation, two factors—tensile strain environment and interfacial orientation of TiN-(220)—help to increase the volumetric percentage of the FE crystals in HfOx. Therefore, two effective methods are proposed to mitigate the wake-up effect in HfZrOx crystals: stress engineering and optimized interface orientation. We report a CMOS-compatible HfZrOx FRAM technology that exhibits a wake-up free character, 1010/109 endurance cycles, extrapolated 10-year retention at 105°C/85°C, and initial Pr = 25/18 μC/cm2 for 2D/3D FRAM. In addition to the performance of the FE device, the design of reliable FE test kits, the retention test pattern for the 1T1C chip, and the trustable estimations of endurance/scalability are discussed. Based on FRAM performance, memory architecture, and the smallest sensible charge, 3D-FRAM technology with an AR of 30 can be scaled up to a 20 nm technology node in a cylindrical structure.

Chapter 1 Introduction 1
1.1 The status about ferroelectric memory 1
1.2 Introduction of HfOx-based ferroelectric material 2
Chapter 2 Literature review 4
2.1 The role of strain in o-phase HfOx 4
2.2 Interfacial studies on M/HfZrOx/M 5
Chapter 3 FRAM Device fabrication and simulation of ferroelectric HfZrOx 11
3.1 FEOL+BEOL fabrication 11
3.1.1 Planar-type FRAM process 12
3.1.2 Trench-type FRAM process 13
3.2 Simulation of ferroelectric HfZrOx 14
Chapter 4 Endurance studies in 2D/3D FRAM. 26
4.1 Test pattern and test-kit design of 1C-FRAM 26
4.2 Benchmark and the engineering approach on 2D/3D-FRAM 32
4.2.1. Benchmark on 2D-FRAM and 3D-FRAM 32
4.2.2. Effects of the tensile stressor and optimal interfacial layer on 2D-FRAM 33
4.2.3 Same engineering concept from 2D-FRAM to 3D-FRAM 37
4.3 Estimation of FRAM in endurance and scaling 50
4.3.1. Estimation with TDDB method and fatigue 50
4.3.2. Scalability: memory window versus technology node 52
4.4 Conclusions 58
Chapter 5 Retention studies in 2D/3D FRAM 59
5.1 Retention test pattern and the worst case 59
5.2 Retention in 2D and 3D FRAM 65
5.3 Conclusions 67
Chapter 6 Conclusions 72
References 74

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