此博士論文探討效能穿隧型電晶體與記憶體元件設計與發展。電晶體部分關注穿隧電晶體元件，深入探索新式非對稱無接面與金屬源極穿隧電晶體之開關機制與元件設計。記憶體部分關注電荷捕捉記憶體元件，深入探索以蕭特基穿隧操作之矽基與鍺基電荷捕捉記憶體其源極側注入機制與元件設計。研究探討以模擬分析進行，研究重點關注低壓操作時元件特性及與標準架構對比時之優勢，以求應用於實際之效能積體電路元件中。
傳統電荷捕捉記憶體元件的汲極側注入存在閘極與汲極場的衝突，需要高閘極和汲極電壓來確保足夠的汲極側注入。若利用鍺基代替矽基，藉由降低垂直注入能障和更大的碰撞游離率，鍺基記憶體元件可進行更有效的汲極側注入。相對而言，採用蕭特基汲源極，可在源極側區域產生陡變的能帶和強烈的電場，對鍺基或矽基記憶體元件皆能在低電壓時更有效地注入熱電子。鍺基電荷捕捉記憶體，若同時運用蕭特基汲源極及鍺基閘極介電層，將可分別優化橫向通道能帶與垂直介電層能帶，實現最有效的注入，成為理想的效能記憶元件。
微縮後的標準型穿隧電晶體元件，會引發嚴重的短通道效應和短汲極效應。藉由所設計的非對稱無接面架構，穿隧電晶體能抑制耦合的短通道與短汲極效應，並提升元件的開關特性和導通電流。而在低電壓工作時，非對稱無接面穿隧電晶體仍能維持優異的次臨界擺幅行為和短通道穩定性，具備適當的導通電流以及抑制的漏電流。若再結合高介電值閘氧層，可進一步提升導通電流並將次臨界擺幅最小化。此可極度微縮之非對稱無接面穿隧電晶體能在超低電壓工作，成為理想的效能電晶體元件。另一方面，具金屬源極的穿隧電晶體元件，提供能帶間穿隧和蕭特基隧穿隧兩種穿隧機制來優化次臨界擺幅和導通傳導特性，其金屬源極功函數和摻雜析離程度，為主要兩項關鍵因子以設計出良好的效能電晶體元件。

This dissertation numerically studies tunneling-based transistor devices and memory cells for energy-efficient applications. The study of transistors focuses on tunnel field-effect transistor (TFET). Two tunneling-based TFET architectures were examined with proposed asymmetric junctionless and metal source. The study of memories concentrates on charge-trapping Flash cells. Source-side injection Schottky barrier tunneling-based charge-trapping Si and Ge cells were investigated against conventional drain-side injection Si and Ge cells. Numerically simulations were perform to elucidate the on-off switching mechanism of transistor devices and the injection and operation of memory cells for use in ultralow-voltage CMOS applications.
Conventional drain-side injection cells endure the conflict of gate-to-drain fields. Both high gate and drain voltages are essential to sustain sufficient drain-side injections. The replacement of Si-body with Ge-body helps to perform the more efficient drain-side injections for the lower transverse barrier and larger impact ionization rate. Relatively, Schottky barrier source/drain cells induces abrupt band-bending and strong field around the source-side regions to efficiently inject hot-electrons at low voltages either in Ge- or Si-body cells. Incorporating Schottky barrier source/drain with Ge-based gate dielectrics, Ge-body charge-trapping cells can separately optimize the lateral channel and transverse dielectric band-bending for most efficient injections, making it as an ideal green cell.
Scaled TFETs suffer from severe short-channel and short-drain effects caused by direct source-to-drain and body-to-drain tunneling. The designed asymmetric junctionless TFETs (AJ-TFETs) can suppress the coupled short-channel and short-drain effects and improve the on-current switching of TFET devices. The voltage-scaled AJ-TFETs retain excellent subthreshold behaviors and short-channel robustness, offering adequate on-current levels along with minimized leakage levels. Incorporating high-k gate dielectrics into the devices enabled extra on-current boosting and swing minimization. The extremely-scaled AJ-TFETs can operate at ultralow voltage as highly promising energy-efficient transistors. Alternatively, combining band-to-band and Schottky barrier tunneling, metal source TFETs (MS-TFETs) offer two tunneling mechanisms to optimize subthreshold switching and on-state conduction. Source workfunction and dopant segregation are two key resorts to tailor the two tunneling paths for favorable energy-efficient transistors.

Contents
Abstract (Chinese) i
Abstract (English) iii
Acknowledgment (Chinese) v
Contents vii
List of Figures ix
List of Tables xxii
Ch. 1 Introduction 1
1.1 Scaling of Operation Voltages in Flash Memories 1
1.2 Low-Voltage Operated Transistors 3
1.3 Advantages of Tunneling Mechanisms 4
1.4 Objectives and Organization 5
Ch. 2 Physical Models in Numerical Simulations 13
2.1 Schottky Barrier Tunneling 13
2.2 Impact Ionization 16
2.3 Injected Gate Currents 17
2.4 Band-to-Band Tunneling Models 19
2.5 TCAD Simulation 21
Ch. 3 Drain-Side Injection Charge-Trapping Memory Cells 31
3.1 Device Structures and Physical Parameters 32
3.2 Conduction Drain Currents 33
3.3 Gate Current and Injection Efficiency 34
3.4 Lateral Distribution of Hot-Electrons and Injection Currents 35
3.5 Ge-Body Cells with Ge-based Gate Dielectrics 36
Ch. 4 Source-Side Injection Charge-Trapping Memory Cells 49
4.1 Device Structures and Physical Parameters 49
4.2 Drain and Gate Currents 51
4.3 Source-Side and Drain-Side Injections 52
4.4 Source-Side Injections in Ge-Body and Si-Body 54
4.5 Ge-Body with Ge-based Gate Dielectrics 55
4.6 Transverse Dielectric Barriers and Lateral Injection Distributions 55
4.7 Energy-Efficient Injections of Ge-Body Cells 57
Ch. 5 Asymmetric Junctionless Tunnel Field-Effect Transistors 79
5.1 Device Structures and Physical Parameters 79
5.2 Short-Channel and Short-Drain Effects in Scaled TFETs 81
5.3 Switching Mechanism of Scaled AJ-TFETs 84
5.4 Gate Dielectrics and Work Function 88
5.5 Voltage Scaling of Short-Channel AJ-TFETs 90
5.6 Operation at Ultralow Gate and Drain Voltages with High-K Dielectrics 92
5.7 Extremely-Scaled AJ-TFETs for Application at Ultralow Voltages 94
Ch. 6 Metal Source Tunnel Field-Effect Transistors 120
6.1 Device Structures and Physical Parameters 120
6.2 Metal/Semiconductor Junctions 122
6.3 Switching Mechanism of MS-TFFTs 123
6.4 Effects of Short Channel and Misaligned Gate 125
6.5 Metal Source with Dopant Segregation 126
6.6 Low Voltage Performance 127
Ch. 7 Conclusions 145
References 148

[1] T. Yamauchi, “Prospect of embedded non-volatile memory in the smart society,” in 2015 IEEE International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), IEEE, 2015. p. 1-2.
[2] International Roadmap for Device and System (IRDS), 2020 edition.
[3] J. Welser, J. W. Pitera, and C. Goldberg, “Future Computing Hardware for AI,” in IEDM Tech Dig., 2018, p.26.
[4] K. Ishimaru, “Future of Non-Volatile Memory -From Storage to Computing-,” in IEDM Tech Dig., 2019, p.11.
[5] K. Matsubara, T. Nagasawa, Y. Kaneda, H. Mitani, T. Iwase, Y. Aoki, K. Hashimoto, T. Morioka, K. Maekawa, T. Ito, H. Kondo, and T. Kono, “A 2T-MONOS Embedded Flash Macro with 65-nm SOTB Technology Achieving 0.15-pJ/bit Read Energy with 80-MHz Access for IoT Applications,” IEEE Solid-State Circuits Lett., vol. 3, pp. 58–61, Mar. 2020.
[6] S. Takagi, M. Noguchi, M. Kim, S.-H. Kim, C.-Y. Chang, M. Yokoyama, K. Nishi, R. Zhang, M. Ke, M. Takenaka, “III-V/Ge MOS device technologies for low power integrated systems,” Solid-State Electron., vol. 125, pp. 82–102, Nov. 2016.
[7] C.-X. Xue and M. F. Chang, “Challenges in Circuit Designs of Nonvolatile-Memory based Computing-in-memory for AI Edge Devices,” in Proc. International SoC Design Conference (ISOCC), pp.164–165, 2019.
[8] K. Nii, Y. Taniguchi, and K. Okuyama, “A Cost-Effective Embedded Nonvolatile Memory with Scalable LEE Flash®-G2 SONOS for Secure IoT and Computing-in-Memory (CiM) Applications,” in Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp.1-4, 2020.
[9] N. Alam and M. Alam, “The Trend of Different Parameters for Designing Integrated Circuits from 1973 to 2019 and Linked to Moore's Law,” Aust. J. Eng. Innov. Technol., vol.2, no. 2, pp.16-23, 2020
[10] C. Kuo, T. Toms, N.M. Weidner, H. Choe, D. Shum, K.-M. Chang, and P. Smith, “A 512 KB flash EEPROM for a 32 bit microcontroller,” in Proc. IEEE Symp. VLSI Technol. Dig. Tech. Papers., Jun. 1991, pp. 87–88.
[11] H. Hidaka, ed., “Embedded flash memory for embedded systems: technology, design for sub-systems, and innovations,” Springer, 2017.
[12] T. Yamauchi, Y. Yamaguchi, T. Kono, and H. Hidaka, “Embedded flash technology for automotive applications,” in IEDM Tech. Dig., 2016, pp. 703–706.
[13] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells - an overview,” Proceedings of the IEEE, vol. 85, no. 8, pp. 1248–1271, Aug. 1997.
[14] R. Benz, E. Camerlenghi, A. Modelli, and A. Visconi, “Introduction to Flash memory,” Proceedings of the IEEE, vol. 91, no. 4, pp. 489–502, Apr. 2003.
[15] S. Lai, “Tunnel oxide and ETOXTM Flash scaling limitation,” in Proc. Int. IEEE Nonvolatile Memory Technol. Conf., 1998, pp. 6–7.
[16] G. Atwood, “Future directions and challenges for ETox Flash memory scaling,” IEEE Trans. Device Mater. Reliab., vol. 4, no. 3, pp. 301–305, Sep. 2004.
[17] G. Molas, D. Deleruyelle, B. De Salvo, G. Ghibaudo, M. Gely, S. Jacob, D. Lafond, and S. Deleonibus, “Impact of few electron phenomena on floating-gate memory reliability,” in IEDM Tech. Dig., 2004, pp. 877–880.
[18] K. Naruke, S. Taguchi, and M. Wada, “Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness,” in IEDM Tech. Dig., 1988, pp. 424–427.
[19] S. Yamada, Y. Hyura, T. Yamane, K. Amemiya, Y. Ohshima, and K. Yoshikawa, “Degradation mechanism of flash EEPROM programming after program/erase cycles,” in IEDM Tech. Dig., 1993, pp. 23–26.
[20] S. Lee, “Scaling Challenges in NAND Flash Device toward 10nm Technology,” in 2012 4th IEEE International Memory Workshop, 2012, pp. 1–4.
[21] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, “NROM: a novel localized trapping, 2-bit nonvolatile memory cell,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 543–545, Nov. 2000.
[22] I. Bloom, P. Pavan, and B. Eitan, “NROMTM–a new non-volatile memory technology: form device and products,” Microelectron. Eng., vol. 59, no. 4, pp. 213–223, Nov. 2001.
[23] A. Shappir, E. Lusky, G. Cohen, I. Bloom, M. Janai, and B. Eitan, “The two-bit NROM reliability,” IEEE Trans. Device Mater. Reliab., vol. 4, no. 3, pp. 397–403, Sep. 2004.
[24] E. lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, “Characterization of channel hot electron injection by the subthreshold slope of NROMTM device,” IEEE Electron Device Lett., vol. 22, no. 11, pp. 556–558, Nov. 2001.
[25] L. Larcher, P. Pavan, and B. Eitan, “On the physical mechanism of the NROM erase,” IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1593–1599, Oct. 2004.
[26] E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, “Electrons retention Model for localized charge in oxide–nitride–oxide (ONO) dielectric,” IEEE Electron Device Lett., vol. 23, no. 9, pp. 556–558, Sep. 2002.
[27] W.-J. Tsai, C.-C. Yeh, N.-K. Zous, C.-C. Liu, S.-K. Cho, T. Wang, S. C. Pan, C.-Y. Lu, “Positive oxide charge-enhanced read disturb in a localized trapping storage Flash memory cell,” IEEE Electron Device Lett., vol. 51, no. 3, pp. 434–439, Mar. 2004.
[28] K. Rupp, “50 years of microprocessor trend data,” Microprocessor Trend Data Repository, https://github.com/karlrupp/microprocessor-trend-data, 2022.
[29] W.-Y. Lu and Y. Taur, “On the Scaling Limit of Ultrathin SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1137-1141, May 2006.
[30] W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Lett., vol. 28, no. 8, pp. 743-745, Aug. 2007.
[31] L. Esaki, “New phenomenon in narrow Germanium p-n junctions,” Phys. Rev., vol. 109, no. 2, pp. 603–604, 1958.
[32] L. Esaki, “Long Journey into Tunneling,” Science, vol. 183, no. 4130, pp. 1149–1155, 1974.
[33] L. Esaki, “Discovery of the tunnel diode,” IEEE Trans. Electron Devices, vol. ED-23, no. 7, pp. 644–647, Jul. 1976.
[34] W. K. Shih, E. X. Wang, S. Jallepalli, F. Leon, C. M. Maziar, and A. F. Tasch. Jr., “Modeling gate leakage current in nMOS structures due to tunneling through an ultra-thin oxide,” Solid-State Electron., vol. 42, no. 6, pp. 997–1006, Jun. 1998.
[35] S. H. Lo, D. A Buchanan, Y. Taur, and W. Wang, “Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's,” IEEE Electron Device Lett., vol. 18, no. 5, pp. 209–211, May 1997.
[36] M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2,” J. Appl. Phys., vol. 40, no. 1, p. 278, 1969.
[37] E. O. Kane, “Theory of tunneling,” J. Appl. Phys., vol. 32, no. 1, p. 83, 1961.
[38] J. M. Larson and J. P. Snyder, “Overview and status of metal S/D Schottky-barrier MOSFET technology,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1048–1058, May, 2006.
[39] S. Zhu, J. Chen, M.-F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du, C. H. Tung, A. Chin, and D. L.Kwong, “N-type Schottky barrier source/drain MOSFET using ytterbium silicide,” IEEE Electron Device Lett., vol. 25, no. 8, pp. 565–567, Aug. 2004.
[40] A. C. Seabaugh and Q. Zhang, “Low voltage tunnel transistors for beyond CMOS logic,” Proceedings of the IEEE, vol. 98, pp. 2095–2110, Dec. 2010.
[41] Q. Zhang, W. Zhao, and S. A. Seabaugh, “Low-subthreshold swing tunnel transistors,” IEEE Electron Device Lett., vol. 27, no. 4, pp. 297–300, Apr. 2006.
[42] By Alan C. Seabaugh, and Qin Zhang, “Low-voltage tunnel transistors for beyond CMOS logic,” Proceedings of the IEEE, vol. 98, no. 12, pp. 2095-2110, Dec. 2010.
[43] TaurusTM Medici User Guide, Synopsys Inc., Mountain View, CA, Mar. 2017.
[44] Sentaurus™ Device User Guide, Synopsys Inc., Mountain View, CA, USA, 2020.
[45] K. Matsuzawa, K. Uchida, and A. Nishiyama, “A unified simulation of Schottky and ohmic contacts,” IEEE Trans. Electron Devices, vol. 47, no. 1, pp. 103–108, Jan. 2000.
[46] M. Ieong, P. M. Solomon, S. E. Laux, H. P. Wong, and D. Chidambarrao, “Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model,” in IEDM Tech. Dig., 1998, pp. 733–736.
[47] C.-K. Huang, W. E. Zhang, and C. H. Yang, “Two-Dimensional Numerical Simulation of Schottky Barrier MOSFET with Channel Length to 10 nm,” IEEE Trans. Electron Devices, vol. 45, no. 4, pp. 842–848, Apr. 1998.
[48] C.-H. Shih and J.-T. Liang, “Nonvolatile Schottky barrier multibit cell with source-side injected programming and reverse drain-side hole erasing,” IEEE Trans. Electron Devices, vol. 57, no. 8, pp. 1774–1780, Aug. 2010.
[49] J. M. Andrews and M. P. Lepselter, “Reverse current–voltage characteristics of metal–silicide Schottky diodes,” Solid-State Electron., vol. 13, no. 7, pp. 1011–1023, Jul. 1970.
[50] S. Xiong, T. J. King, and J. Bokor, “A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain,” IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1859–1867, Aug. 2005.
[51] Sze, S. M., and G. I. Gibbons. “Avalanche breakdown voltages of abrupt and linearly graded p‐n junctions IN Ge, Si, GaAs, and GaP,” Appl. Phys. Lett., vol. 8, no. 5, pp. 111-113, Aug. 1966.
[52] S. Selberherr, “Analysis and simulation of semiconductor devices,” Springer Science & Business Media, 1984.
[53] W. Shockley, “Problems related to p-n junctions in silicon,” Czechoslov. J. Phys., vol. 11, no.2, pp.81-121, 1961.
[54] P. A. Wolff, "Theory of electron multiplication in silicon and germanium," Phys. Rev., vol. 95, no. 6, pp. 1415-1420, 1954.
[55] T. Y. Chan, P.-K. Ko, and C. Hu, “A simple method to characterize substrate current in MOSFETs,” IEEE Electron Device Lett., vol. EDL-5, no. 12, pp. 505–507, Dec. 1984.
[56] S. Tam, P.-K. Ko, and C. Hu, “Lucky-electron model of channel hot electron injection in MOSFET's,” IEEE Trans. Electron Devices, vol. 31, no. 9, pp. 1116–1125, Sep. 1984.
[57] K. Hasnat, C.-F. Yeap, S. Jallepalli, W.-K. Shih, S. A. hareland, V. M. Agostinelli, Jr., A. F. Tasch, Jr., and C. M. Maziar, “A pseudo-lucky electron model for simulation of electron gate current in submicron MOSFET's,” IEEE Trans. Electron Devices, vol. 43, no. 8, pp. 1264–1273, Aug. 1996.
[58] E. O. Kane, “Zener tunneling in semiconductors,” J. Phys. Chem. Solids, vol. 12, no. 2, pp. 181-188, Jan. 1959.
[59] W. G. Vandenberghe, B. Sorée, W. Magnus, and G. Groeseneken, “Zener tunneling in semiconductors under nonuniform electric fields,” J. Appl. Phys., vol. 107, no. 5, pp. 054 520-1–054 520-3, Mar. 2010.
[60] C.R.Crowell, “The Richardson constant for thermionic emission in Schottky barrier diodes,” Solid-State Electron.,vol. 8, no. 4, pp. 395-399, Apr.1965.
[61] S. M. Sze, “The Physics of Semiconductor Devices,” second ed., Willey, New York, 1981.
[62] M. V. Fischetti and S. E. Laux, “Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys,” J. Appl. Phys., vol. 80, no. 4, pp. 2234–2252, Aug. 1996.
[63] K.-H. Kao, A. S. Verhulst, W. G. Vandenberghe, B. Sorée, G. Groeseneken, and K. D, Meyer, “Direct and indirect band-to-band tunneling in Germanium-based TFETs,” IEEE Trans. Electron Devices, Vol. 59, no. 2, pp. 292-301, Feb. 2012.
[64] Virginia Semiconductor, “The General Properties of Si, Ge, SiGe, SiO2 and Si3N4,” June 2002.
[65] D. Fleetwood, Sokrates Pantolides, and Ronald D. Schrimpf, “Defects in Microelectronic Materials and Devices,” CRC Press, 2008.
[66] P. Broqvist, J. F. Binder, and A. Pasquarello, “Band offsets at the Ge/GeO interface through hybrid density functionals,” Appl. Phys. Lett., vol. 94, no. 14, p. 141911, Apr. 2009.
[67] T. Mikawa, S. Kagawa, T. Kaneda, Y. Toyama, and O. Mikami, “Crystal orientation dependence of ionization rates in germanium,” Appl. Phys. Lett., vol. 37, no. 4, pp.387-389, 1980.
[68] Y. Kamata, “High-k/Ge MOSFETs for Future Nanoelectronics,” Materials today, vol. 11, p. 30-38, Jan.-Feb. 2008.
[69] M. Caymax, G. Eneman, F. Bellenger, C. Merckling, A. Delabie, G. Wang, R. Loo, E. Simoen, J. Mitard, B. De Jaeger, G. Hellings, K. De Meyer, M. Meuris, and M. Heyns, “Germanium for advanced CMOS anno 2009: A SWOT analysis,” in IEDM Tech. Dig., 2009, pp. 461.
[70] Patrick S. Goley and Mantu K. Hudait, “Germanium Based Field-Effect Transistors: Challenges and Opportunities,” Materials, vol. 7, no. 3, pp. 2301-2339, Mar. 2014.
[71] K. J. Kuhn, “Considerations for Ultimate CMOS Scaling,” IEEE Trans. Electron Devices, vol. 59, no. 7, pp. 1813–1828, Jul. 2012.
[72] D. Kuzum, A. J. Pethe, T. Krishnamohan and K. C. Saraswat, “Ge (100) and (111) N and P-FETs with high mobility and low-T mobility characterization,” IEEE Trans. Electron Devics, vol. 56, no. 4, pp. 185-192, Apr. 2009.
[73] Y.-C. Chou, C.-W. Tsai, C.-Y. Yi, W.-H. Chung, S.-Y. Wang, and C.-H. Chien, “Used for Neuro-Inspired-in-Memory Computing Using Charge-Trapping MemTransistor on Germanium as Synaptic Device,” IEEE Trans. Electron Devics, vol. 67, pp. 3605-3609, Sep. 2020.
[74] J. Lee, B.-G. Park, and Y. Kim, “Implementation of Boolean Logic Functions in Charge Trap Flash for In-Memory Computing,” IEEE Electron Device Lett., vol. 40, pp. 1358-1361, Sep. 2019.
[75] H.-K. Fang , K.-S. Chang-Liao, K.-C. Chou, T.-C. Chao, J.-E. Tsai, Y.-L. Li, W.-H. Huang, C.-H. Shen, and J.-M. Shieh, “Impacts of Electrical Field in Tunneling Layer on Operation Characteristics of Poly-Ge Charge-Trapping Flash Memory Device,” IEEE Electron Device Lett., vol. 36, pp. 1314-1317, Dec. 2020.
[76] W.-H. Huang, J.-M. Shieh, C.-H. Shen, T.-E. Huang, H.-H. Wang, C.-C. Yang, T.-Y. Hsieh, J.-L. Hsieh, and W.-K. Yeh, “Junction-less poly-Ge FinFET and charge-trap NVM fabricated by laser-enabled low thermal budget processes,” Appl. Phys. Lett., vol. 108, 243502, June 2016.
[77] Z.-H. Ye, K.-S. Chang-Liao, L.-J. Liu, J.-W. Cheng, and H.-K. Fang, “Enhanced Programming and Erasing Speeds of Charge-Trapping Flash Memory Device With Ge Channel,” IEEE Electron Device Lett., vol. 36, pp. 1314-1317, Dec. 2015.
[78] Y. Igura, H. Matsuoka, and E. Takeda “New device degradation due to “cold” carriers created by band-to-band tunneling,” IEEE Electron Devices Lett., vol. 10, no. 5, pp. 227–229, May. 1989.
[79] A. Datta, P. Bharath Kumar, and S. Mahapatra, “Dual-Bit/Cell SONOS Flash EEPROMs: impact of channel engineering on programming speed and bit coupling effect,” IEEE Electron Device Lett., vol. 28, pp. 446–448, May 2007.
[80] C.-H. Shih, J.-T. Liang, and Y.-X. Luo, “Reading operation and cell scalability of nonvolatile Schottky barrier multibit charge-trapping memory cells,” IEEE Trans. Electron Devices, vol. 59, no. 6, pp. 1599–1606, Jun. 2012.
[81] K. Uchida, K. Matsuzawa, J. Koga, S. Takagi, and A. Toriumi, “Enhancement of hot-electron generation rate in Schottky source metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 76, no. 26, pp. 3992–3994, Jun. 2000.
[82] C.-H. Shih, W. Chang, W.-F. Wu, and C. Lien, “Multi-level Schottky barrier nanowire SONOS memory with ambipolar N- and P-channel cells,” IEEE Trans. Electron Devices, vol. 59, no. 6, pp. 1614–1620, Jun. 2012.
[83] W. Chang, C.-H. Shih, Y.-X. Luo, J.-K. Hsia, W.-F. Wu, and C. Lien, “A localized two-bit/cell nanowire SONOS memory using Schottky barrier source-side injected programming,” IEEE Trans. Nanotechnol., vol. 12, no. 9, pp. 760-765, Sep. 2013.
[84] J. M. Andrews and M. P. Lepselter, “Reverse current-voltage characteristics of metal-silicide Schottky diodes,” Solid-State Electron., vol. 13, no. 7, pp. 1011–1023, Jul. 1970.
[85] D. H. Morris, U. E. Avci, K. Vaidyanathan, H. Liu, T. Karnik, I. A. Young, “Novel TFET circuits for high-performance energy-efficient heterogeneous MOSFET/TFET logic,” in 2017 Proc. Symp. VLSI Technology, Systems and Application, IEEE, Apr. 2017.
[86] S. Ahmad, S. A. Ahmad, M. Muqeem, N. Alam, and M. Hasan, “TFET-based robust 7T SRAM cell for low power application,” IEEE Trans. Electron Devices, vol. 66, no. 9, pp. 3834–3840, Sep. 2019.
[87] D. E. Nikonov and I. A. Young, “Overview of beyond-CMOS devices and a uniform methodology for their benchmarking,” Proceedings of the IEEE, vol. 101, no. 12, pp. 2498-2533, Dec. 2013.
[88] A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, vol. 479, pp. 329-337, Nov. 2011.
[89] H. Lu and A. Seabaugh, “Tunnel field-effect transistors: state-of-the-art,” IEEE J. Electron Devices Soc., vol. 2, pp. 44-49, Jul. 2014.
[90] E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeo, “Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications,” J. Appl. Phys., vol. 103, p. 104504, May 2008.
[91] K. Alam, “Orientation engineering for improved performance of a Ge-Si heterojunction nanowire TFET,” IEEE Trans. Electron Devices, Vol. 64, pp. 4850-4855, Dec. 2017.
[92] M. Noguchi, S.H. Kim, M. Yokoyama, O. Ichikawa, T. Osada, M. Hata, S. Takagi, ”High Ion/Ioff and low subthreshold slope planar-type InGaAs tunnel field effect transistors with Zn-diffused source junctions,” J. Appl. Phys. Vol. 118, 045712, 2015.
[93] C.-H. Shih and N. D. Chien, “Sub-10-nm tunnel field-effect transistor with graded Si/Ge heterojunction,” IEEE Electron Device Lett., vol. 32, no. 11, pp. 1498-1500, Nov. 2011.
[94] N. D. Chien, C.-H. Shih, H.-J. Teng, and C.-K. Pham, “Dependence of short-channel effects on semiconductor bandgap in tunnel field-effect transistors,” J. Phys. Conf. Ser., vol. 1034, no.1, p. 012003, May 2018.
[95] C.-Y. Hsu, C.-Y. Chang, E. Yi Chang, C. Hu, “Suppressing non-uniform tunneling in InAs/GaSb TFET with dual-metal gate,” IEEE J. Electron Devices Soc., vol. 4, pp. 60-65, Mar. 2016.
[96] M.-J. Lee, W.-Y. Choi, “Effects of device geometry on hetero-gate-dielectric tunneling field-effect transistors,” IEEE Electron. Device Lett. vol. 33, pp. 1459–1461, Oct. 2012.
[97] M. G. Bardon, H. P. Neves, R. Puers, and C. V. Hoof, “Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions,” IEEE Trans. Electron Devices, vol. 57, pp. 827-834, Apr. 2010.
[98] L. Liu, D. Mohata, and S. Datta, “Scaling length theory of double-gate interband tunnel field-effect transistors,” IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 902-908, Apr. 2012.
[99] N. D. Chien and C.-H. Shih, “Short-channel effect and device design of extremely scaled tunnel field-effect transistors,” Microelectronics Reliability, Vol. 55, pp. 31-37, Jan. 2015.
[100] Y.-H. Chen, N. D. Chien, J.-J. Tsai, Y.-X. Luo, and C.-H. Shih, “Short-drain effect of 5 nm tunnel field-effect transistors,” in 2015 Silicon Nanoelectronics Workshop (SNW), 2015. pp. 57-58
[101] K. Boucart and A. M. Ionescu, “Length scaling of the double gate tunnel FET with a high-k gate dielectric,” Solid-State Electron., vol. 51, no. 11/12, pp. 1500-1507, Nov./Dec. 2007.
[102] C.-H. Shih and N. V. Kien, “Sub-10-nm asymmetric junctionless tunnel field-effect transistors,” IEEE J. Electron Devices Soc., vol. 2, pp. 128-132, Sep. 2014.
[103] Y.-H. Chen, H-J. Teng, C.-H. Lien and C.-H. Shih, “Device operation and physical mechanism of asymmetric junctionless tunnel field-effect transistors designed to suppress coupled short-channel/short-drain effects and promote on-current switching for ultralow-voltage CMOS applications,” Semicond. Sci. Technol., vol. 37, no.6, p. 065007, Jun 2022.
[104] A. Seabaugh, “The Tunneling Transistor,” IEEE Spectrum, vol. 50, vo. 10, pp. 35-62, 2013.
[105] C. Anghel, P. Chilagani, A. Amara, and A. Vladimirescu, “Tunnel field effect transistor with increased ON current, low-k spacer and high-k dielectric,” Appl. Phys. Lett. , Vol. 96, no. 12, pp. 122104-122104-3, Mar. 2010.
[106] K. Boucart and A. M. Ionescu, “Double-gate tunnel FET with high-κ gate dielectric,” IEEE Trans. Electron Devices, vol. 54, no. 7, pp. 1725-1733, Jul. 2007.
[107] A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken, “Tunnel field-effect transistor without gate-drain overlap,” Appl. Phys. Lett., vol. 91, no. 5, p. 053102, Jul. 2007.
[108] A. Chattopadhyay and A. Mallik, “Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor,” IEEE Trans. Electron Devices, Vol. 58, no. 3, pp. 677-683, Mar. 2011.
[109] C.-H. Shih and N. D. Chien, “Physical operation and device design of short-channel tunnel field-effect transistors with graded silicon-germanium heterojunctions,” J. Appl. Phys., vol. 113, pp. 134507-134507-7, Apr. 2013.
[110] N. D. Chien, C.-H. Shih, and L. T. Vinh, “Drive current enhancement in tunnel field-effect transistors by graded heterojunction approach,” J. Appl. Phys., vol. 114, pp. 094507-094507-6, Sep. 2013.
[111] C.-H. Shih and N. D. Chien, “Physical properties and analytical models of band-to-band tunneling in low-bandgap semiconductors,” J. Appl. Phys., vol. 115, pp. 014507-014507-7, Jan. 2014.
[112] C.-H. Shih and N. D. Chien, “Design and modeling of line-tunneling field-effect transistors using low bandgap semiconductors” IEEE Trans. Electron Devices, vol. 61, no. 6, pp. 1907-1913, Jun. 2014.
[113] C.-H. Shih, T.-S. Kang, Y.-H. Chen, Hung-Jin Teng and Nguyen Dang Chien, “Dopant-Segregated Metal Source Tunnel Field-Effect Transistors with Schottky barrier and band-to-band Tunneling,” in 2017 Silicon Nanoelectronics Workshop (SNW), IEEE, 2017, p. 53-54.
[114] Z. Jiang, Y.-Q. Zhuang, C. Li, P. Wang and Y.-Q. Liu, “Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor,” Chin. Phys. B, vol. 25, no. 2, p. 027701, Feb. 2016.
[115] S. Sant, A. Schenk, K. Moselund, and H Riel.,“Impact of Trap-assisted Tunneling and Channel Quantization on InAs/Si Hetero Tunnel FETs” in 74th Annual Device Research Conference (DRC), IEEE, Newark, DE, 2016.
[116] F. Horst, A. Farokhnejad, B. Iñíguez and A. Kloes,“Closed-Form Modeling Approach of Trap-Assisted Tunneling Current for Use in Compact TFET Models” in 26th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES), IEEE,Rzeszow, Poland, 2019.
[117] H. Ibach and H. Lüth, “Solid-State Physics: An Introduction to Principles of Materials Science,” Springer Science & Business Media , 2009.
[118] T. Topuria, N. D. Browning and Z. Ma, “Characterization of ultrathin dopant segregation layers in nanoscale metal-oxide-semiconductor field effect transistors using scanning transmission electron microscopy,” Appl. Phys. Lett., vol. 83, no. 21, pp. 4432–4434, Nov. 2003.
[119] J. Knoch, M. Zhang, Q. T. Zhao, St. Lenk, and S. Mantl, “Effective Schottky barrier lowering in silicon-on-insulator Schottky-barrier metal-oxide-semiconductor field-effect transistor using dopant segregation,” Appl. Phys. Lett., vol. 87, no. 26, pp. 263505-1–263505-3, Dec. 2005.
[120] A. Kinoshita, “Dopant-segregated source/drain technology for high-performance CMOS,” in Proc. Int. Conf. Solid-State Integr. Circuit Technol., 2008, pp. 150–152.
[121] A. Kinoshita, “Dopant segregated Schottky S/D and application to high performance MOSFETs,” in Proc. Int. Workshop Junction Technol., 2009, pp. 34–37.
[122] Y. T. Huang, P. W. Liu, W. T. Chiang, T. L. Tsai, C. H. Tsai, C. T. Tsai, and G. H. Ma, “Schottky source/drain CMOS device optimization with dopant-segregated NiPt silicide,” in Proc. Int. Symp. VLSI Technol. Syst. Appl., 2008, pp. 38–39.
[123] W.-Y Loh, P. Y. Hung, B. E. Coss, P. Kalra, Injo Ok, Greg Smith, C.-Y. Kang, S.-H. Lee, J. Oh, B. Sassman, P. Majhi, P. Kirsch, H-H. Tseng, and R. Jammy, “Selective phase modulation of NiSi using n-ion implantation for high performance dopant-segregated source/drain n-channel MOSFETs,” in VLSI Symp. Tech. Dig., 2009, pp. 100–101.