近年來半導體產業發展迅速，高科技電子產品的需求逐漸增加，應用也日益廣泛，為追求產品外型輕薄短小，攜帶方便，符合目前電子產品的個人化需求，將一個完整的系統包括記憶體以及周邊的邏輯電路等製作在同一個晶片上的系統單晶片（System-on-a-chip, SoC）整合製程逐漸受到重視，此製程方式能有效的減少成本與製造時間。
本論文提出一種新型的P通道可多次寫入非揮發性記憶體，其最大的特點為完全相容於16奈米CMOS鰭式場效電晶體（FinFET）的先進邏輯製程。此新型元件將互補資料儲存於兩個浮動閘極，能夠在同一顆元件中讀取電流差，並藉由接觸點與金屬閘極間的電容進行側向耦合。在製程微縮至奈米級別的現在，閘極介電層逐漸變薄造成浮動閘極儲存電子的能力不足，利用差動式結構擴大感測範圍，同時提出一個全面性的自我修復機制，當讀取範圍明顯縮小時，透過週期性的自我修復操作來解決資料保存性的問題。
新型P通道差動式記憶體元件的編程效率高，且在經過寫入抹除的循環測試後，表現出優越的穩定性與可靠性，同時擁有良好的抗干擾特性，再加上特殊的自我修復機制，能夠解決現今閘極介電層太薄引發資料流失現象而導致的可靠度問題，這些優點使此元件有較高的競爭力。

In recent years, the semiconductor technology advances rapidly. The demand for high-tech electronic products increases rapidly. People began to pursue product, which is small, light and easy-to-carry. In order to meet these needs, a system-on-a-chip (SoC) integration of a complete system including memories and logic circuits on the same chip of great interests to computation. This process can effectively reduce the cost and developmental time.
A new differential p-channel multiple-time programmable (MTP) memory cell is proposed. Its most important feature is its fully compatible with advanced 16nm CMOS FinFET logic process. This differential MTP cell stores complementary data in floating gates coupled by slot contact structure enable different read current on a single cell. In nano-scale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charge inside the floating gates for very long time. By using a differential architecture, the sensing window of the cell can be extended and maintained by a new blanket boost scheme. Charge retention problem in floating gate cells can be improved by periodic restoring lost charge when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturb immunity.

摘要 i
Abstract ii
致謝 iii
內容目錄 iv
附圖目錄 vi
附表目錄 viii
第一章 序論 1
1.1 非揮發性記憶體介紹與應用 2
1.2 浮動閘極記憶體的介紹與應用 3
1.3 邏輯非揮發性記憶體簡介 4
1.4 論文大綱 4
第二章 可多次寫入記憶體之簡介 9
2.1 可多次寫入記憶體之特性與應用 9
2.2 載子注入之操作機制 10
2.3 可多次寫入記憶體回顧與發展 12
2.4 小結 13
第三章 新型P通道差動式側向耦合記憶體元件結構與操作原理 16
3.1 新型P通道記憶體元件結構介紹 16
3.2 差動式記憶體之特點與操作流程 18
3.3 新型P通道記憶體元件操作機制與原理 19
3.4 小結 22
第四章 新型P通道差動式側向耦合記憶體元件之特性分析 35
4.1 差動式記憶體元件基本操作特性分析 35
4.2 記憶體元件可靠度分析 38
4.3 可靠度最佳化及自我修復 41
4.4 N通道與P通道特性討論 43
4.5 小結 44
第五章 結論 64
參考文獻 65

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