隨著物聯網的到來，低功耗、高寫入速度的記憶體元件逐漸受到大眾消費者的關注。另外，對電晶體的通道長度做微縮的現況下，許多提升元件的效能被提出來，除了結構上的改變，改變通道材料的想法也被提出。
本論文建構出雙閘極蕭特基能障源/汲極的O-N-O電荷捕捉式記憶體，並將之與雙閘極的傳統摻雜源/汲極的O-N-O電荷捕捉式記憶體比較。發現蕭特基能障元件的注入效率較傳統型元件高出許多。另外也透過文獻的比較，來估計出兩種記憶體元件的寫入時間：在VDS為3V，VGS為6V時，蕭特基元件為45.7us；在VDS為6V，VGS為6V時，傳統元件為68.7us，速度上確實是蕭特基元件快了33%。另一方面，在同樣是雙閘極金屬蕭特基能障源/汲極的結構中，我們比較了矽通道和不同組成比例的矽鍺（Si1-xGex）通道的注入效率。發現若是固定金屬的功函數為4.27eV時，矽鍺的注入效率大於矽的注入效率，並且以x=0.7時為最高；而若是固定蕭特基能障高度為0.2eV時，則是矽通道元件擁有較高的注入效率，矽鍺通道元件的注入效率則是隨著x比例增加而減少。

Since the coming of IoT era, low power consumption, high program speed memory device gains lots of interest. Moreover, the ongoing scaling on transistor channel length results not only in new structure strategy, but also in the replacement issue of channel material.
In this thesis, we establish the structure of double gate Schottky barrier source/drain O-N-O charge trapping memory cell (SBC), and compare it with double gate conventionally doped source/drain O-N-O charge trapping memory cell (CVC). We find that SBC has higher injection efficiency than CVC does. Additionally, we also compare the above devices with some existing references, and estimate the program time. At VDS=3V, VGS=6V, the program time of SBC is 45.7us. At VDS=6V, VGS=6V, the program time of CVC is 68.7us. SBC is 33% faster than CVC. Also, in the same double gate SB source/drain structure, we compare injection efficiency between Si channel and different x ratio of Si1-xGex channel. At fixed metal workfunction m=4.27eV, injection efficiency is higher in SiGe channel, especially at x=0.7. At fixed SB height b0=0.2eV, Si channel device has higher injection efficiency, injection efficiency decrease with increasing x in SiGe channel device.

摘要 i
Abstract ii
致謝 iii
內文目錄 iv
圖目錄 vi
表目錄 viii
第1章 ：序論 1
1.1 前言 1
1.1.1 浮動閘極（Floating Gate）型記憶體介紹 3
1.1.2 矽-二氧化矽-氮化矽-二氧化矽-矽（SONOS）型記憶體介紹 4
1.2 蕭特基能障金氧半場效電晶體 5
1.3 研究動機 6
1.4 論文架構 7
第2章 ：電荷捕捉式記憶體的操作與物理模型 11
2.1 SONOS型快閃記憶體操作方式 11
2.1.1 福勒－諾德漢穿隧（Fowler-Nordheim Tunneling）之機制 12
2.1.2 通道熱電子注入（CHEI）之機制 15
2.1.3 帶對帶穿隧引發熱電洞注入（BBHHI）之機制 19
2.2 蕭特基能障電流穿隧之機制 21
第3章 ：蕭特基能障記憶體之基本電性模擬 24
3.1 模擬軟體介紹 24
3.2 元件基本模型 27
3.2.1 單閘極元件與雙閘極元件的比較 27
3.2.2 蕭特基能障接面 30
3.2.3 雙閘極蕭特基能障型記憶體基本結構 32
3.3 雙閘極蕭特基能障記憶體的電性與寫入分析 34
3.3.1 雙閘極蕭特基能障型記憶體基本電性分析 34
3.3.2 熱電子寫入實驗設計 39
第4章 ：矽鍺通道之雙閘極蕭特基能障記憶體之模擬 44
4.1 矽鍺之材料參數 44
4.2 矽通道與矽鍺通道之雙閘極蕭特基能障記憶體之基本電性比較 45
4.3 矽通道與矽鍺通道之雙閘極蕭特基能障記憶體之寫入比較 52
第5章 ：總結與未來展望 54
5.1 結論 54
5.2 未來展望 55
參考文獻 56

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