隨著網路應用與資訊產業的蓬勃發展，各種社交網絡資料的傳輸頻寬需求增加，人們對於數據傳輸速度及傳輸量的需求呈現爆炸性成長，因此超高速與低成本的相關元件及系統急遽增加。而傳輸速度為4×25 Gb/s的系統，此規格已成為現今市面可見的產品。此傳輸線的接頭包含光電轉換元件及電路，與傳輸電訊號之系統進行光電轉換，再利用低損耗高頻寬且低干擾的光纖(fiber)取代傳統的電纜進行多通道訊號傳輸。
第二章中，我們使用65nm製程設計應用於光調變器的分散式放大器，傳輸速度達到60 Gb/s並擁有高達4.2 Vpp的擺幅輸出，其中使用Stacked-FET架構來避免因高擺幅產生的gate-oxide崩潰問題，Stacked-FET架構有許多需要注意的設計考量都在此章節中一一介紹。
第三章中，我們使用40nm製程設計分散式放大器，並沿用上一章節的Stacked-FET架構解決崩潰問題，使用Shunt-Series Peaking來補償因此架構損失的頻寬，Shunt-Series Peaking理論分析也在此章節中介紹，整體電路頻寬表現高達53 GHz，擺幅在50 Gbaud/s時高達4.2 Vpp。
第四章中，我們透過PAM-4合成電路將兩組不同的OOK訊號合成為PAM-4訊號，並將此電路與分散式放大器結合，也使用Stacked-FET架構解決崩潰問題，其中頻率補償架構使用Series Peaking，整體電路以28nm製程製作，由於此製程為數位邏輯製程，沒有提供Thick Metal，頻寬會被限制，電路頻寬表現45GHz，擺幅在50 Gbaud/s時亦有3.7 Vpp的輸出。
第五章中，不同於前些章節使用的分散式放大器，我們使用簡易的差動放大器配合並以Buffer隔離Pre-Driver與Main-Driver的電容，利用SiGe 0.13µm的高速特性設計出頻寬高達77 GHz與80 Gbaud/s時高達4.8 Vpp的輸出擺幅。
第六章中，我們將介紹未來方向以及上述電路能夠改進的地方。

With the explosive development of web applications and information industry, the increasing demands of transmission bandwidth for the various social networks, and the explosive of data transmission and processing, the demand of transmission speed in communication systems has grown rapidly recently. One recent specification targets the transmission speed up to 4×25 Gb/s. The optical communication front end module includes optoelectronics deivces, ampilfier and connector, so that the signal can be transmitted by light.
In chapter 2, 65nm technology was used to design a modulator driver that using Stack-FET as gain cell which can transmit 60 Gb/s data with 4.2 Vpp output. Stacked-FET prevent gate-oxide breakdown due to large output signal. Several design consideration are discussed also in this chapter.
In chapter 3, 40nm technology is used to design a modulator driver that using distributed amplification and Stacked-FET as its gain cell. To compensate the bandwidth loss due to Stacked-FET, Shunt-Series Peaking technique is uesd. Further discussions are also in this chapter. The bandwidth of the circuit is 53 GHz and has 4.2 Vpp output when 50 Gbaud/s signal is transmitted.
In chapter 4, a PAM-4 combiner is used to combin two different OOK signal to a PAM-4 signal. We put distributed amplifer which also has Stacked-FET as its gain cell and PAM-4 conbiner together to form the whole circuir. It is designed in 28nm digital process which Thick Metal is not provided. Its bandwidth reaches 45 GHz and 3.7 Vpp output when 50 Gbaud/s signal is transmitted.
In chapter 5, unlike the circuit above, simple differential pairs are used to design a modulator driver. Buffers are also used to divide the capacitance of Pre-Driver and Main-Driver. With the advantage of high speed in SiGe 0.13µm technology, the circuit can reach 77 GHz bandwidth and up to 4.8Vpp output in the speed of 80 Gbaud/s.
In chapter 6, the conclusions are given with the recommendation of future works.

第1章 緒論 1
1.1 研究背景與基本介紹 1
1.2 論文架構 4
第2章 使用65NM CMOS 設計應用於光通訊調變驅動器之60GB/S分散式放大器 5
2.1 分散式放大器挑戰 5
2.2 GAIN CELL 架構 5
2.3 STACKED-FET 架構設計考量 8
2.3.1 Biasing Resistor Ri大小 8
2.3.2 Ci大小 11
2.4 STACKED-FET 架構與CASCODE架構比較 12
2.5 SHUNT-PEAKING 14
2.6 電感 17
2.7 PROPOSED GAIN CELL 18
2.8 模擬與量測結果 19
2.9 結論 22
第3章 運用SHUNT-SERIES PEAKING之50 GBAUD/S分散式放大器 23
3.1 動機 23
3.2 SHUNT-SERIES PEAKING TECHNIQUE 23
3.3 PROPOSED GAIN CELL 25
3.4 模擬結果 28
3.4.1 頻域模擬 28
3.4.2 時域模擬 29
3.5 結論 31
第4章 50GAUD/S PAM-4 訊號合成功能之光調變器驅動電路 32
4.1 動機 32
4.2 PAM4合成 32
4.3 PROPOSED GAIN CELL 35
4.4 整體電路架構 37
4.5 模擬結果 38
4.5.1 頻域模擬 38
4.5.2 時域模擬 40
4.6 結論 41
第5章 80GBAUD/S MODULATOR DRIVER IN SIGE 0.13UM 42
5.1 動機 42
5.2 PRE-DRIVER 42
5.3 MAIN-DRIVER 44
5.4 PROPOSED CIRCUIT 45
5.5 模擬結果 46
5.5.1 頻域模擬 46
5.5.2 時域模擬 47
5.6 結論 49
第6章 結論 50
6.1 總結 50
6.2 未來工作 51
參考文獻 52

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