為了產生更高速的資料傳輸速度，近年來許多研究者進行操作於微波頻段的系統與電路開發。考慮了所使用的製程能力(90-nm CMOS process)以及實際應用上，K頻段的電路設計是最適合我們設計的。在K頻段的眾多應用，又以24 GHz的汽車雷達最廣為人知，故此論文以24 GHz為設計頻率。
除了提升操作頻率外，調變的不同方式亦可提升資料傳輸速度，OFDM 即為其中常見的調變方式之一。然而，OFDM 調變會伴隨著高峰值比的問題。所以設計給OFDM使用的電路不只需要注意最佳功率時的表現也要關心平均功率下的表現。可惜的是一般的功率放大器在平均功率下的表現欠佳，使得提升平均功率下的表現的相關技術廣泛研究，其中Doherty為此技術中常見的電路架構之一。因此，Doherty也為此論文中主要研究之架構。
本論文中提出了兩個操作於24GHz的Doherty 功率放大器。因為傳統架構上需要使用四分之一波長傳輸線實現輸出阻抗轉換以及相位補償之用，然而它的物理長度在K頻段會造成面積過大的問題。故為改善它，在第一個晶片中捨棄四分之一波長傳輸線使用直接匹配的方式來省下晶片面積。結果上，此晶片以0.975 平方公釐實現電路，另外，量測結果上有最佳效率28%, 6-dB 輸出倒退效率12%，以及超過18-dBm的飽和輸出功率。而第二顆晶片設計上則是以第一顆的想法上為基底，加入適應性偏壓電路以加強前者的輸出功率以及線性度表現。就量測結果而言，這晶片有最佳效率21%，6-dB 輸出倒退效率12%，以及將近19.5-dBm的飽和輸出功率。

To obtain higher data rate transmission, many people focused on researches of microwave systems and circuits design in recent years. Considering about the ability of utilized process (90-nm CMOS process) and practical applications, we thought that K-band is the suitable choice. Moreover, among the various applications in K-band, the design of 24GHz vehicle radar is widely known. Thus, we decided 24GHz as our designed frequency.
Besides employing the higher operation frequency to get faster data rata communication, it could achieve by the advanced modulation schemes, like the OFDM. However, there is high PAPR issue for OFDM system. Therefore, the circuits used in OFDM system have to be concerned about the performances at not only peak power level but also average power level. Unfortunately, for typical PA design, there is obvious performance degradation in average power level. To improve it, many researches proposed the advanced PA structures, such as Doherty PA. Further, it is the primary topic in this thesis.
In this thesis, we presented two Doherty PAs operated at 24GHz. In conventional structure, quarter-wavelength T-line is utilized for load modulation and phase compensation. Nonetheless, the physical length of K-band quarter-wavelength T-line could lead to area issue. In work A, we proposed that employing the direct matching method rather than the traditional one to shrink the layout area. As result, we realized it with merely 0.975 mm2.Additonally, there are maximum PAE 28%, 6-dB OBO PAE 12%, and more than 18-dBm saturated output power in measurement results. For work B, we based on the concept of work A and added the adaptive bias network to enhance the output power and linearity of previous circuit. This work has peak PAE 21%, 6-dB OBO PAE 12%, and approximately 19.5-dBm saturated output power.

摘要 i
ABSTRACT ii
Contents i
List of Figures vi
List of Tables xvii
Chapter 1 Introduction 19
1.1. Backgrounds 19
1.2. K-Band Standards and Applications 19
1.3. Thesis Organization 21
Chapter 2 CMOS Integrated Components Design 22
2.1. Active Devices 22
2.2. Passive Devices 25
2.2.1 Capacitors 25
2.2.1.1 MOM Capacitors 26
2.2.1.2 MIM Capacitors 27
2.2.2 Transmission Lines (T-lines) 28
2.2.2.1 Induction to the geometries of T-lines 28
2.2.2.2 Specifications of T-lines 29
2.2.2.3 Applications from T-lines 30
2.2.3 Inductors 31
2.2.3.1 Specifications of inductors 32
2.2.3.2 Design consideration 34
2.2.4 Wilkinson Power Dividers 37
2.2.4.1 Conventional Architecture 37
2.2.4.2 Modified Architecture 41
Chapter 3 Fundamentals of Power Amplifiers 44
3.1. Introduction to Power Amplifiers 44
3.2. Design considerations for Power Amplifiers 44
3.2.1 S-Parameters and Stability 44
3.2.1.1 S-Parameters 44
3.2.1.2 Stability 46
3.2.2 Output Power 49
3.2.3 Power Gain 50
3.2.4 Efficiency 50
3.2.4.1 Drain Efficiency 50
3.2.4.2 Power Added Efficiency (PAE) 51
3.2.5 Linearity 51
3.2.5.1 Gain Compression and Harmonic Distortion 52
3.2.5.2 Intermodulation 54
3.2.5.3 AM/PM Conversion 56
3.3. Selection of Optimal Load Impedance 57
3.3.1 Load Line Theory 58
3.3.2 Load-Pull Simulation 60
3.4. Classification of Power Amplifiers 61
3.4.1 Class A 62
3.4.2 Class AB and Class B 63
3.4.3 Class C 64
3.4.4 Comparisons and Conclusions 65
3.5. Introduction of Common Power Amplifier Topologies 70
3.5.1 Cascode 70
3.5.2 Cascade 71
3.6. Design Flow of Power Amplifiers 74
3.7. Considerations for MOS size and bias setting 76
3.8. Literature Survey of K-Band Power Amplifiers 79
Chapter 4 Fundamentals of Doherty Power Amplifiers 83
4.1. Motivations on Designing Doherty Power Amplifiers 83
4.2. Introduction to Doherty Power amplifiers 86
4.2.1 Introduction to Doherty Power Amplifiers Architecture 87
4.2.2 Derivation of Classical Doherty power Amplifiers 90
4.3. Literature Survey of Doherty Power Amplifiers 101
4.3.1 Symmetric and Asymmetric Doherty PA 102
4.3.2 Three-way Doherty PA 106
4.3.3 Transformer-based Doherty PA 115
4.4. Linearity Improvement Techniques 119
4.4.1 Differential structure 119
4.4.2 Inductive Source Degeneration 123
4.4.3 Adaptive Bias Technique 127
4.5. Comparisons between Doherty and Combining PAs 128
Chapter 5 K-Band Doherty Power Amplifier with Direct Matching Method for Chip Size Reduction and Compact K-Band Doherty Power Amplifier with Adaptive Bias Network 133
5.1. Motivations 133
5.1.1 Work A: K-Band Doherty Power Amplifier with Direct Matching Method for Chip Size Reduction 133
5.1.2 Work B: Compact K-Band Doherty Power Amplifier with Adaptive Bias Network 134
5.2. Paper Survey 134
5.2.1 Offset Line Technique 135
5.2.1.1 Offset line in carrier PA 135
5.2.1.2 Offset line in peaking PA 137
5.2.2 TLLM Architecture 141
5.2.2.1 Two-point matching 141
5.2.2.2 Two-sided matching 143
5.2.3 Adaptive Biasing Network 147
5.3. Circuit Design 150
5.3.1 Design Flow 151
5.3.2 Core Circuit Design of Work A 152
5.3.2.1 Power Amplifiers Design 153
5.3.2.2 Output Matching Network Design 155
5.3.2.3 Transmission Line Design 161
5.3.2.4 Input Matching Network and Wilkinson Power Divider Design 163
5.4. Simulation and Measurement Results of Work A 166
5.4.1 Layout Consideration 166
5.4.2 Simulation and Measurement results 168
5.4.3 Summary 174
5.5. Core Circuit Design of Work B 176
5.5.1.1 Power Amplifier Design 176
5.5.1.2 Adaptive Bias Network Design 180
5.5.1.3 Output Matching Network Design 183
5.5.1.4 Input Matching Network and Wilkinson Power Divider Design 189
5.6. Simulation and Measurement Results of Work B 193
5.6.1 Layout Consideration 193
5.6.2 Simulation and Measurement results 195
5.6.3 Summary 208
5.7. Conclusions 216
Chapter 6 Conclusions and Future Works 220
Reference 223

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