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作者(中文):謝宜君
作者(外文):Hsieh, Yi-Chun.
論文名稱(中文):毫米波鎖相迴路電路設計與分析
論文名稱(外文):Design and Analysis of Circuit Blocks in Millimeter-Wave Phase-Locked Loop
指導教授(中文):劉怡君
指導教授(外文):LIU, YI-CHUN
口試委員(中文):朱大舜
李俊興
口試委員(外文):CHU, TA-SHUN
Li, Chun-Hsing
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學號:104063538
出版年(民國):107
畢業學年度:106
語文別:英文
論文頁數:120
中文關鍵詞:鎖相迴路震盪器多頻帶除頻器
外文關鍵詞:PLLVCOMulti-bandILFD
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早期因為CMOS元件操作頻率的限制,毫米波大多使用III-V族元素的元件,但III-V族元素的元件成本比較高,使毫米波電路普及受到限制。隨著半導體產業的發展,縮小電晶體的面積同時也提高了截止頻率,與III-V族元素的元件相比較低的成本,使毫米波電路的普遍率上升。而在毫米波電路之中,鎖相迴路是一個很重要的部分,除了應用於通訊系統,還可應用於同步處理及影像感測中。在生活實用上,除了國防安全之外,行動通訊、液晶顯示器、車用雷達也隨著經濟的快速發展而有大量的需求。
本論文探討了鎖相迴路之中的電路區塊,主要分為震盪器,除頻器以及相位頻率偵測器。第一個設計為操作在11-30 GHz的 多頻段震盪器,利用90奈米互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor, CMOS)製程實現。調頻範圍分別為15.7%、12.4%、9.9%和7.5%。而在同時可以看到四個頻段的情況下,在1 MHz的相位雜訊為-89 dBc/Hz到-92 dBc/Hz。總共消耗40.3 mW。第二個設計為操作在V頻帶除以二的除頻器。可除範圍為12 GHz,消耗4.69 mW,其對輸入訊號相位雜訊的改善大約為6 dB,也是利用90奈米互補式金屬氧化物半導體製程實現。第三個設計為兩個鎖相迴路系統中的電流型邏輯電路(Current-Mode Logic)、可編程分頻器(Programmable Divider Chain)以及相位頻率偵測器,兩個鎖相迴路系統分別操作於W 以及兆赫波頻段,使用90奈米互補式金屬氧化物半導體製程及40奈米互補式金屬氧化物半導體製程實現。總共消耗63.86 mW (在90奈米互補式金屬氧化物半導體製程)和58.2 mW (在40奈米互補式金屬氧化物半導體製程)。
In early times, due to the operating frequency limitation of CMOS process, millimeter wave circuits are usually realized by III-V semi-conductor technologies, but the cost of III-V semi-conductors is expensive, which lead the limited popularity of the millimeter-wave systems and circuits. With the development of semi-conductor industry, the size of MOS transistor is smaller and the cut-off frequency increases in the meanwhile. Compared with the cost of III-V semi-conductors, the lower cost of CMOS technology makes millimeter wave more popular. In millimeter-wave, phase-locked loop (PLL) is an important circuit. In addition to communication system, PLLs can also be applied in image sensors. With the fast development of economics, besides national security, PLL is of great demands in mobile communication, LCD monitors, and automotive radars.
In this thesis, the circuit blocks in PLLs are discussed, mainly the VCO (Voltage-Controlled Oscillator), Dividers and PFD (Phase Frequency Detector). The first design is a multi-band VCO operated at 11-30 GHz in TSMC 90-nm CMOS. The tuning range of four band is 15.7%, 12.4%, 9.9% and 7.5%, respectively. While four band output can be seen simultaneously, the phase noise at 1-MHz offset is -89 dBc/Hz to -92 dBc/Hz, and the total power consumption is 40.3 mW. The second design is a divided-by-two ILFD (Injection-Locked Frequency Divider) operated at V-band in TSMC 90-nm CMOS. The locking range is 12 GHz and power dissipation is 4.69 mW. The improvement of phase noise from the input signal is about 6 dB. The last designs are CML (Current-Mode Logic), programmable divider chain and PFD in two PLLs, which these two PLLs are operated at W-band in TSMC 90-nm CMOS and THz in TSMC 40-nm CMOS. The total consumption power in these two PLLs is 63.86 mW (in 90-nm CMOS) and 58.2 mW (in 40-nm CMOS), respectively.
摘要 i
ABSTRACT ii
Contents iii
List of Figures vi
List of Tables xiii
Chapter 1 Introduction 1
1.1. Background 1
1.2. Thesis Organization 2
Chapter 2 Passive Devices in CMOS Process 3
2.1. Capacitors 3
2.1.1 MOM Capacitors 3
2.1.2 MIM Capacitors 4
2.2. Varactors 6
2.3. Inductors 9
2.3.1 Basic Concept 9
2.3.2 Non-Ideal Inductor Model 10
2.4. Transformers 18
2.4.1 Basic Concept 18
2.4.2 Non-Ideal Transformer Model 19
Chapter 3 Phase-Locked Loop Fundamentals 25
3.1. System Models of PLLs 25
3.1.1 Type-I PLLs 25
3.1.2 Type-II PLLs 27
3.1.2.1 2nd Order PLL with 1st Order Loop Filter 28
3.1.2.2 3rd Order PLL with 2nd Order Loop Filter 30
3.1.2.3 4th Order PLL with 3rd Order Loop Filter 32
3.1.3 Noise Analysis 33
3.2. Design of LC Tank Oscillators 35
3.2.1 Linear Model of Oscillators 35
3.2.2 Tuning Range 38
3.2.3 Phase Noise 40
3.3. Design of Injection-Locked Frequency Dividers 49
3.3.1 Analysis of Injection Locking 49
3.3.2 Equivalent Model of ILFDs 51
3.4. Others Circuit Blocks 52
3.4.1 Phase Frequency Detectors 52
3.4.2 Charge Pumps 54
Chapter 4 A 11-30-GHz Multi-Band Switched-Transformer VCO in 90-nm CMOS 56
4.1. Overall Circuit Architecture 56
4.2. Class-C Oscillator 57
4.3. Proposed Switched Inductors 59
4.4. Proposed Transformer 62
4.5. Simulation and Measurement Results 70
4.6. Conclusions 80
Chapter 5 A 70-GHz Divided by 2 Injection-Locked Frequency Divider in 90-nm CMOS 85
5.1. Overall Circuit Architecture 85
5.2. Proposed Inductor 86
5.3. Analysis of Locking Range 88
5.4. Simulation and Measurement Results 92
5.5. Conclusions 97
Chapter 6 A 94-GHz Signal Source Generator in 90-nm CMOS & A 330-GHz Signal Source Generator in 40-nm CMOS 99
6.1. Overall Circuit Architecture 99
6.1.1 A 94-GHz Signal Source 99
6.1.2 A 330-GHz Signal Source 99
6.2. CML 100
6.3. Programmable Divider Chain 103
6.4. Phase Frequency Detector 105
6.5. Simulation Results 107
6.6. Conclusions 113
Chapter 7 Conclusions and Future Works 115
Reference 117
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