近年來，非揮發性記憶體相當普及並且應用極廣，也增加了高速度、低能量消耗、低成本元件的需求。伴隨著製程微縮與科技的進步，上個世代的主流非揮發性記憶體-快閃記憶體，遇到了低儲存單元電流、高臨界電壓飄移與耦合雜訊干擾等等的問題。許多新世代的非揮發興記憶體擁有潛力可以解決這些問題。而接觸點電阻式記憶體(Contact ReRAM)具有低寫入功耗、快速寫入時間、以及具有邏輯製成相容性，這些特性對產業界而言，極具吸引力與競爭力。然而，接觸點電阻式記憶體有著小阻值率(高阻值/低阻值)以及阻值高偏移問題，使得讀取增加許多困難。
我們提出具臨界電壓補償架構之小偏移參考電流產生器，來增加感測放大器輸入端的電壓差距。在輸入電壓由10uA至60uA的範圍，透過臨界電壓補償架構，我們可以使電流偏移量縮小了2.8倍至4.2倍，且無須耗費多於的讀取時間。此外，在位元線長度為512時，相比於開啟4顆參考細胞並使用傳統電流鏡，我們提出的小偏移電流鏡可以加速讀取1.17倍，相比於開啟1顆參考細胞，我們的架構可以加速讀取1.54x。
我們在1Mb 電阻式隨機存取記憶體實現我們的小偏移參考電流產生器，此專案於台積電65奈米標準CMOS製程下製作。藉由我們的小偏移參考電流產生器，在位元線長度為512時，量測電阻式隨機存取記憶體之讀取時間可以達到3.0ns。

Recently, non-volatile memory (NVM) is popular and used in many applications, which requirements for higher performance, lower power and low cost. However, as technology shrinks, flash memories, the mainstream of NVM in last century, face the challenges, such as small cell current, large variation of threshold voltage and coupling noise. Many emerging non-volatile memories have great potential to overcome those problems and to replace the flash memory. CRRAM features low write voltage, short program time and logic-process compatibility, and make CRRAM attractive to industry. However, small R-Ratio (RHRS/RLRS) and variation of resistance lead to the difficulties in read.
We proposed a small offset reference generator with Threshold-Voltage Compensation Scheme by enlarging the difference of input current in sense amplifier. The offset suppression is about 2.8x~4.2x smaller across 10uA to 60uA of input current by our threshold voltage compensated scheme, which with zero timing overhead in read operation. In addition, we can achieve 1.17x faster speed than the conventional CM with 4 activated replica cells and can achieve 1.54x than with 1 activated replica cell at BL-Length=512.
We implement our proposed small offset reference generator into a 1Mb ReRAM macro fabricated in TSMC 65nm CMOS process. The measured read access time can achieve3.0ns by our proposed scheme at BL-Length=512.

摘要 i
Abstract ii
致謝 iii
Contents iv
List of Figures vii
List of Tables x
Chapter 1 Introduction 1
1.1 Memory in SoC products 1
1.2 Memory Landscape 2
1.2.1 RAM 4
1.2.2 CAM 4
1.2.3 ROM 5
1.2.4 Programmable NVMs 5
1.3 Challenges of Flash Memory in Advanced Technology 6
1.4 Emerging Non-Volatile Memories 9
Chapter 2 Characteristic of Contact-ReRAM 12
2.1 Structure of Contact-ReRAM 12
2.2 Switching Mechanism 14
2.3 Writing Operation 15
2.4 Reading Operation 16
Chapter 3 Design Challenges of ReRAM Read 18
3.1 Issues of CRRAM 18
3.2 Threshold Voltage in Process 19
3.3 Sensing Schemes 20
3.3.1 Structure and Operation of Conventional Sensing Schemes 20
3.3.2 Previous Arts 23
3.4 Reference Current Generator 26
3.4.1 Conventional Reference Current Generator 26
3.4.2 Previous Work 28
3.5 Current Mirror 32
3.5.1 Current Mirrors 33
3.5.2 Previous Work 34
Chapter 4 Proposed Circuits Schemes and Analysis 39
4.1 Proposed Small Offset Current Mirror 39
4.1.1 Threshold Voltage Compensation 39
4.1.2 Structure of Proposed Current Mirror 39
4.1.3 Operation of Proposed TVC-CM 41
4.1.4 Structure of Reference Generation 45
4.2 Analysis and Comparison 46
4.2.1 Design Consideration 46
4.2.2 Offset Comparison 48
4.2.3 Comparison of Reference current distribution 50
4.2.4 Comparison of Speed 51
Chapter 5 Measurement Results and Conclusion 53
5.1 CRRAM Macro 53
5.2 Design for Testchip 55
5.2.1 DFF Clock 55
5.2.2 Test-mode of Current Mirror 57
5.3 Measured Performance 58
5.4 Conclusions and Future Work 64
Reference 66

[1] Kiyoo Itoh, Takayasu Sakurai, “VLSI Memory Chip Design”, Springer-Verlag, NY, pp. 1-46, Apr. 2001.
[2] A. Allan; D. Edenfeld; W. H. Joyner; A. B. Kahng; M. Rodgers; Y. Zorian Computer ITRS, “2001 Technology Roadmap For Semiconductors,” IEEE Computer, vol. 35, issue 1, pp. 42–53, Jan. 2002.
[3] Francesco Menichelli, Mauro Olivieri, “Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, issue 2, pp. 161-171, Jan. 2009.
[4] A. G. Hanlon, "Content-Addressable and Associative Memory Systems a Survey," Electronic Computers, IEEE Transactions on , vol.EC-15, issue 4, pp.509-521, Aug. 1966
[5] C. C. Wang, C. J. Cheng, T. F. Chen and J. S. Wang, "An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices," in IEEE Journal of Solid-State Circuits, vol. 44, no. 5, pp. 1571-1581, May 2009.
[6] J. Li, R. K. Montoye, M. Ishii and L. Chang, “1 Mb 0.41 µm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing,” IEEE Journal of Solid-State Circuits, vol. 49, Issue 4, pp. 896-907, April. 2014.
[7] M. F. Chang, C. C. Lin, A. Lee, C. C. Kuo, G. H. Yang, H. J. Tsai, T. F. Chen, S. S. Sheu, P. L. Tseng, H. Y. Lee, T. K. Ku, “A 3T1R Nonvolatile TCAM Using MLC ReRAM with Sub-1ns Search Time,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 1-3, Feb. 2015.
[8] D. Smith, J. Zeiter, T. Bowman, J. Rahm, B. Kertis, A. Hall, S. Natan, L. Sanderson, R. Tromp, J. Tsang, “A 3.6ns 1Kb ECL I/O BiCMOS U.V. EPROM,” IEEE International Symposium on Circuits and Systems, vol. 3, pp. 1987-1990, May 1990.
[9] C. Kuo, M. Weidner, T. Toms, H. Choe, K. M. Chang, A. Harwood, J. Jelemensky, P. Smith, “A 512-kb flash EEPROM embedded in a 32-b microcontroller,” IEEE Journal of Solid-State Circuits, vol. 27, Issue 4, pp. 574-582, Apr. 1992.
[10] S. H. Kulkarni, Z. Chen, J. He, L. Jiang, M. B. Pedersen, K. Zhang, “A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μm2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS,” IEEE Journal of Solid-State Circuits, vol. 45, Issue 4, pp. 863-868, Apr. 2010.
[11] Y. H. Tsai, H. M. Chen, H. Y. Chiu, H. S. Shih, H. C. Lai, Y. C. King, C. J. Lin, “45nm Gateless Anti-Fuse Cell with CMOS Fully Compatible Process,” IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 95-98, Dec. 2007.
[12] Webfeet Inc., “Semiconductor industry outlook,” Non-Volatile Memory Conference, Santa Clara, CA., 2002
[13] S. L. Min, E. H. Nam, “Current trends in flash memory technology,” IEEE Asia and South Pacific Conference on Design Automation, pp. 24-27, Jan. 2006.
[14] F. Masuoka, M. Momodomi, Y. Iwata, R. Shirota, "New ultra high density EPROM and flash EEPROM with NAND structure cell," IEEE International Electron Devices Meeting Digest of Technical Papers, vol. 33, pp. 552-555, 1987.
[15] A. Bergemont, H. Haggag, L. Anderson, E. Shacham, G. Wolstenholme, "NOR virtual ground (NVG)-a new scaling concept for very high density flash EEPROM and its implementation in a 0.5 um process," IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 15-18, Dec. 1993.
[16] R. Bez, E. Camerlenghi, A. Modelli, A. Visconti, "Introduction to Flash Memory," Proceeding of the IEEE, vol. 91, Issue 4, pp. 489-502, April 2003.
[17] Y. Koh, “NAND Flash Scaling beyond 20nm,” IEEE Internstional Memory Workshop, pp. 1-3, May 2009.
[18] K. Prall, “Scaling Non-Volatile Memory Below 30nm,” IEEE Non-Volatile Semiconductor Memory Workshop, pp. 5-10, Aug. 2007.
[19] S. Lee, "Scaling Challenges in NAND Flash Device toward 10nm Technology," IEEE International Memory Workshop, pp. 1-4, May 2012.
[20] J. Jang, H. S. Kim, W. Cho, H. Cho, J. Kim, S. I. Shim, Y. Jang, J. H. Jeong, B. K. Son, D. W. Kim, K. Kim, J. J. Shim, J. S. Lim, K. H. Kim, S. Y. Yi, J. Y. Lim, D. Chung, H. C. Moon, S. Hwang, J. W. Lee, Y. H. Son, U. I. Chung,W. S. Lee, "Vertical cell array using TCAT technology for ultra high density NAND flash memory," IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 192-193, June 2009.
[21] T. Maeda, K. Itagaki, T. Hishida, R. Katsumata, M. Kito, Y. Fukuzumi, M. Kido, H. Tanaka, Y. Komori, M. Ishiduki, J. Matsunami, T. Fujiwara, H. Aochi, Y. Iwata, Y. Watanabe, “Multi-stacked 1G cell/layer Pipe-shaped BiCS flash memory,” IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 16-18, June 2009.
[22] J. Kim, A. J. Hong, S. M. Kim, E. B. Song, J. H. Park, J. Han, S. Choi, D. Jang, J. T. Moon, K. L.Wang, “Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive),” IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 186-187, June 2009.
[23] C. Villa, D. Vimercati, S. Schippers, E. Confalonieri, M. Sforzin, S. Polizzi, M. La Placa, C. Lisi, A. Magnavacca, E. Bolandrina, A. Martinelli, V. Dima, A. Scavuzzo, B. Calandrino, N. Del Gatto, M. Scardaci, F. Mastroianni, M. Pisasale, A. Geraci, M. Gaibotti, M. Sali., “A 125 MHz burst-mode flexible read-while-write 256 Mbit 2b/c 1.8V NOR flash memory,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 52–54, Feb. 2005.
[24] C. Deml, M. Jankowski, C. Thalmaier, “A 0.13µm 2.125MB 23.5ns Embedded Flash with 2GB/s Read Throughput for Automotive Microcontrollers,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 11-15, Feb. 2007.
[25] M. Sako, Y. Watanabe, T. Nakajima, J. Sato, K. Muraoka, M. Fujiu, F. Kouno, M. Nakagawa, M. Masuda, K. Kato, Y. Terada, Y. Shimizu, M. Honma, A. Imamoto, T. Araya, H. Konno, T. Okanaga, T. Fujimura, X. Wang, M. Muramoto, M. Kamoshida, M. Kohno, Y. Suzuki, T. Hashiguchi, T. Kobayashi, M. Yamaoka, R. Yamashita, “A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 22-26, Feb. 2015.
[26] C. H. Hung, M. F. Chang, Y. S. Yang, Y. J. Kuo, T. Ne. Lai, S. J. Shen, J. Y. Hsu, S. N. Hung, H. T. Lue, Y. H. Shih, S. L. Huang, T. W. Chen, T. S. Chen, C. K. Chen, C. Y. Hung, C. Y. Lu, “Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations,” IEEE Journal of Solid-State Circuits, vol. pp, Issue 99, pp. 1-11, Apr. 2015.
[27] D. Kang et al., "256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 130-131, Feb. 2016.
[28] H. Noguchi et al., "4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 132-133, Feb. 2016.
[29] G. D. Sandre, L. Bettini, A. Pirola, L. Marmonier, M. Pasotti, M. Borghi, P. Mattavelli, P. Zuliani, L. Scotti, G. Mastracchio, F. Bedeschi, R. Gastaldi, R. Bez, "A 90nm 4Mb embedded phase-change memory with 1.2V 12ns read access time and 1MB/s write throughput," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 268-269, Feb. 2010.
[30] D. Takashima, Y. Nagadomi and T. Ozaki, "A 100MHz Ladder FeRAM Design with Capacitance-Coupled-Bitline (CCB) Cell," IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 227-228, June 2010.
[31] W. Otsuka, K. Miyata, M. Kitagawa, K. Tsutsui, T. Tsushima, H. Yoshihara, T. Namise, Y. Terao, K. Ogata, “A 4Mb conductive-bridge resistive memory with 2.3GB/s read-throughput and 216MB/s program-throughput,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 210-211, Feb. 2011.
[32] K. Aratani, K. Ohba, T. Mizuguchi, S. Yasuda, T. Shiimoto, T. Tsushima, T. Sone, K. Endo, A. Kouchiyama, S. Sasaki, A. Maesaka, N. Yamada, and H. Narisawa, “A Novel Resistance Memory with High Scalability and Nanosecond Switching,” IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 10-12, Dec. 2007.
[33] Y. H. Tseng, C. E. Huang, C. H. Kuo, Y. D. Chih, C. J. Lin, “High density and ultra small cell size of Contact ReRAM (CR-RAM) in 90nm CMOS logic technology and circuits,” IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 1-4, Dec. 2009.
[34] C. H. Ho, E. K. Lai, M. D. Lee, C. L. Pan, Y. D. Yao, K. Y. Hsieh, Rich Liu, C. Y. Lu, “A Highly Reliable Self-Aligned Graded Oxide WOx Resistance Memory: Conduction Mechanisms and Reliability,” IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 228-229, June 2007.
[35] M. J. Lee, Y. Park, B. S. Kang, S. E. Ahn, C. Lee, K. Kim, Wenxu. Xianyu, G. Stefanovich, J. H. Lee, S. J. Chung, Y. H. Kim, C. S. Lee, J. B. Park, I. G. Baek, I. K. Yoo,” 2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications,” IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 771-774, Dec. 2007.
[36] H. Y. Lee, P. S. Chen, T. Y. Wu, Y. S. Chen, C. C. Wang, P. J. Tzeng, C. H. Lin, F. Chen, C. H. Lien, M.-J. Tsai, “Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based ReRAM,” IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 1-4, Dec. 2008.
[37] B. Gao, S. Yu, N. Xu, L.F. Liu, B. Sun, X.Y. Liu, R.Q. Han, J.F. Kang, B. Yu, Y.Y. Wang, "Oxide-based ReRAM switching mechanism: A new ion-transport-recombination model," IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 1-4, Dec. 2008.
[38] C. H. Wang, Y.H. Tsai, K.C. Lin, M.F. Chang, Y.C. King, C.J Lin "Three-dimensional 4F2 ReRAM cell with CMOS logic compatible process," IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 29.6.1-29.6.4, Dec. 2010.
[39] Y. S. Chen, H. Y. Lee1, P. S. Chen, P. Y. Gu1, C. W. Chen, W. P. Lin, W. H. Liu, Y. Y. Hsu, S. S. Sheu, P. C. Chiang, W. S. Chen, F. T. Chen, C. H. Lien, M.-J. Tsai, " Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity," IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 1-4, Dec. 2009.
[40] G. Bersuker, D. C. Gilmer, D. Veksler, J. Yum, H. Park, S. Lian, L. Vandelli, A. Padovani, L. Larcher, K. McKenna, A. Shluger, V. Iglesias, M. Porti, M. Nafría, W. Taylor, P. D. Kirsch, R. Jammy, "Metal oxide ReRAM switching mechanism based on conductive filament microscopic properties," IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 19.6.1-19.6.4, Dec. 2010.
[41] J. Lee, J. Shin, D. Lee, W. Lee, S. Jung, M. Jo, J. Park, K. P. Biju, S. Kim, S. Park, H. Hwang, "Diode-less nano-scale ZrOx/HfOx ReRAM device with excellent switching uniformity and reliability for high-density cross-point memory applications," IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 19.5.1-19.5.4, Dec. 2010.
[42] C. Cagli, D. Ielmini, F. Nardi and A. L. Lacaita, "Evidence for threshold switching in the set process of NiO-based ReRAM and physical modeling for set, reset, retention and disturb prediction," IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 1-4, Dec. 2008.
[43] Y. H. Tseng, W. C. Shen, C. E. Huang, C. J.Lin, Y. C. King, "Electron trapping effect on the switching behavior of contact ReRAM devices through random telegraph noise analysis," IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 28.5.1-28.5.4, Dec. 2010.
[44] B. Lee and H.S. Philip Wong, "NiO resistance change memory with a novel structure for 3D integration and improved confinement of conduction path," IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 28-29, June 2009.
[45] S. Song, J. H. Yi, W. S. Kim, J. S. Lee, K. Fujihara, H. K. Kang, J. T. Moon, M. Y. Lee, "CMOS device scaling beyond 100 nm," IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 235-238, Dec. 2000.
[46] Jean-Pierre Colinge, Cynthia A. Colinge, “Physics of Semiconductior Devices.” Springer-Verlag, NY, pp. 175-182, 2002.
[47] E. Morifuji, A. Oishi, K. Miyashita, S. Aota, M. Nishigori, H. Ootani, T. Nakayama, K. Miyamoto, F. Matsuoka, T. Noguchi, M. Kakumu, "A 1.5 V high performance mixed signal integration with indium channel for 130 nm technology node," IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 459-462, Dec. 2000.
[48] C. H. Shih, Y. M. Chen and C. Lien, "Effect of insulated shallow extension for the improved short-channel effect of sub-100 nm MOSFET," International Semiconductor Device Research Symposium, pp. 158-159, Dec. 2003.
[49] S. Seven, K. G. Anil, J. B. Pawl, R. Duffy, K. Henson, R. Lindsay, A. Lauwers, A. Veloso, J. F. de Mameffe, J. Ramos, R. A. Camilla-Castillo, P. Eyben, C. Dachs,W. Vandervost, M. Jurczak, S. Biesemans, K. De Meyer, "Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices," IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 99-102, Dec. 2004.
[50] M. F. Chang, S. J. Shen, C. C. Liu, C. W. Wu, Y. F. Lin, S. C. Wu, C. E. Huang, H. C. Lai, Y. C. King, C. J. Lin, H. J. Liao, Y. D. Chih, H. Yamauchi, "An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 206-208, Feb. 2011.
[51] M. Jefremow, T. Kern, W. Allers, C. Peters, J. Otterstedt, O. Bahlous, K. Hofmann, R. Allinger, S. Kassenetter, D. Schmitt-Landsiedel, "Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 216-217, Feb. 2013.
[52] C. Kim, K. Kwon, C. Park, S. Jang and J. Choi, "A covalent-bonded cross-coupled current-mode sense amplifier for STT-MRAM with 1T1MTJ common source-line structure array," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 1-3, Feb, 2015,.
[53] J. Javanifard, T. Tanadi, H. Giduturi, K. Loe, R. L. Melcher, S. Khabiri, N. T. Hendrickson, A. D. Proescholdt, D. A. Ward, M. A. Taylor, "A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 424-624, Feb. 2008.
[54] M. Qazi, K. Stawiasz, L. Chang and A. Chandrakasan, "A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 350-351, Feb. 2010.
[55] B. Giridhar, N. Pinckney, D. Sylvester, D. Blaauw, "A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 242-243, Feb. 2014
[56] Sripriya R Bandi and P. R. Mukund, "A Compensation Technique for Transistor mismatch in current mirror," IEEE International SOC Conference, Sept. 2004.
[57] G. Wegmann and E. A. Vittoz, "Analysis and improvements of accurate dynamic current mirrors," IEEE Journal of Solid-State Circuits, vol. 25, pp. 699-706, 1990.
[58] M. F. Chang, S. J. Shen and C. C. Liu, U.S. Patent No. 8169255, May 2012
[59] M. F. Chang, Y. F. Lin and Y. C. Liu," An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast Read Embedded Flash Macros," IEEE Journal of Solid-State Circuits, vol. 50, pp. 2188-2198, 2015.
[60] Behzad Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed. New York: McGraw-Hill College, 2016.
[61] S. Dietrich, M. Angerbauer, M. Ivanov, D. Gogl, H. Hoenigschmid, M. Kund, C. Liaw, M. Markert, R. Symanczyk and G. Mueller, “A nonvolatile 2-Mbit CBRAM memory core featuring advanced read and program control,” IEEE J. Solid-State Circuits, vol. 42, pp. 839-845, Apr. 2007.
[62] M. F. Chang and S. J. Shen, “A process variation tolerant embedded split-gate Flash memory using pre-stable current sensing scheme,” IEEE J. Solid-State Circuits, vol. 44, pp. 987-994, Mar. 2009.
[63] M. Durlam, P. J. Naji, A. Omair and M. DeHerrera, “A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects,” IEEE J. Solid-State Circuits, vol. 38, pp. 769-773, May 2003.
[64] R. Takemura, T. Kawahara, K. Miura and H. Yamamoto, “A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and „1‟ / „0‟ Dual-Array Equalized Reference Scheme,” IEEE J. Solid-State Circuits, vol. 45, pp. 869-879, Apr. 2010.
[65] C. Kim, K. Kwon, C. Park, S. Jang and J. Choi, "A covalent-bonded cross-coupled current-mode sense amplifier for STT-MRAM with 1T1MTJ common source-line structure array," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 1-3, Feb, 2015,.
[66] B. Q. Le, M. Achter, C. Chin Ghee, G. Xin, L. Cleveland, C. Pau-Ling, M. Van Buskirk, and R. W. Dutton, “Virtual-ground sensing techniques for a 49-ns/200-MHz access time 1.8-V 256-Mb 2-bit-per-cell flash memory,” IEEE J. Solid-State Circuits, vol. 39, pp. 2014-2023, Nov. 2004.
[67] C. P. Lo et al., "Embedded 2Mb ReRAM macro with 2.6ns read access time using dynamic-trip-point-mismatch sampling current-mode sense amplifier for IoE applications," 2017 Symposium on VLSI Circuits, Kyoto, 2017, pp. C164-C165.