由於高速傳輸資料的需求日益增加，人們提高操作頻率以增加頻寬，因此射頻(Radio Frequency, RF)收發機變得非常重要，其應用包含雷達、高速通訊和生醫影像傳輸等等，其中雷達應用有汽車防撞系統、衛星通訊與雷達測速槍，根據歐洲電信標準協會(ETSI)與聯邦通信委員會(FCC)所定義的頻段，24GHz 射頻收發機受到 業 界 的 青 睞 。 在 射 頻 收 發 機 中 ， 包 含 低 雜 訊 放 大 器(LNA) 、 振 盪 器(Oscillator)、混頻器(Mixer)、天線(Antenna)和功率放大器(PA)，本論文針對功率放大器特性的改善作為主要的討論。
本論文共有四個晶片，第一個晶片針對匹配電路的損耗及晶片面積做出改善，提出一個無輸出匹配電路之堆疊式功率放大器，由於毋需輸出匹配電路，因此可以改善電路的特性，量測結果，飽和輸出功率16.7 dBm，最佳功率附加效率18%，在1-dB 增益壓縮點，輸出功率12.3 dBm，功率附加效率8.1 %。第二個晶片則是改善第一顆晶片的線性度與效率，藉由加入適應性偏壓電路，減少低功率模態的電流，量測結果，飽和輸出功率17.6 dBm，最佳功率附加效率25.3%，在1-dB 增益壓縮點，輸出功率為13.2 dBm，功率附加效率11.5 %，1-dB 增益壓縮點回推 6 -dB 之功率附加效率為 7 %。第三和四個晶片使用功率結合器以增加最大輸出功率，並且加入適應性偏壓電路，提出一個四路堆疊式功率放大器暨適應性偏壓電技術，其模擬結果得到飽和輸出功率24.4 dBm，最佳功率附加效率18.5%，在1-dB 增益壓縮點，輸出功率 23.2 dBm，功率附加效率14%。

Due to the increasing demands for high speed data transmission, it is appealing to shift up the operating frequency for its wide bandwidth. Various applications such as collision avoidance system, satellite communication and radar speed gun are used widely. According to the frequency defined by European Telecommunications Standards Institute (ETSI) and US Federal Communications Commission (FCC), a 24-GHz radio frequency (RF) transceiver is attractive to industry. RF transceiver consists of low noise amplifier (LNA), oscillator, mixer, antenna and power amplifier (PA). In this thesis, the goal is to improve the circuit performance of PA.
There are four works in the thesis. In Work A, to improve loss produced by matching network and reduce chip area, a K-band stacked PA without output matching network is presented. Thanks to non-output matching network in PA design, the circuit performance is enhanced obviously. It achieves saturation output power Psat is 16.7 dBm and PAEpeak is 18 %. At 1-dB compression point, OP1dB and PAE1dB are 12.3 dBm and 8.1%, respectively. In Work B, it is designed to improve the linearity and efficiency of Work A. The current in low power mode is reduced through an adaptively biased network. In the measurement results, Psat is 17.6 dBm and PAEpeak is 25.3 %. At 1-dB compression point, OP1dB and PAE1dB are 13.2 dBm and 11.5 %, respectively. PAE at the 6-dB backoff from P1dB is around 7 %. To increase maximum output power, a transformer is used to combine power in Work C and D. In the simulation results, Psat is 24.4 dBm and PAEpeak is 18.5 %. At 1-dB compression point, OP1dB and PAE1dB are 23.2 dBm and 14 %, respectively.

摘要 i
ABSTRACT ii
Contents i
List of Figures iv
List of Table xi
Chapter 1 Introduction 1
1.1. Motivation 1
1.2. K-band Regulations 2
1.3. K-band Literature Survey 3
1.4. Thesis Organization 6
Chapter 2 Overview of Power Amplifier 7
2.1. Introduction 7
2.2. Important Parameters of Power Amplifier 8
2.2.1 Output Power 8
2.2.2 Efficiency 9
2.2.3 Linearity 10
2.2.4 Stability 14
2.2.5 Optimum Load Impedance of Power Amplifier 16
2.3. Linearization Technique 18
2.3.1 Doherty PA 18
2.3.2 Pre-distortion Technology 19
2.3.3 Adaptively Biased Technology 20
Chapter 3 90-nm CMOS Process 21
3.1. Active Device 21
3.2. Passive Device 23
3.2.1 Inductor 23
3.2.2 Transformer 28
Chapter 4 A K-Band Stacked Power Amplifier without Output Matching Network in 90-nm CMOS 33
4.1. Paper Survey 33
4.1.1 Compare to Cascode and Stacked Structure 33
4.2. Circuit Design 35
4.2.1 Design Flow 35
4.2.2 Core Circuit 36
4.3. Simulation and Measurement Results 49
4.3.1 Discussion 56
4.3.2 Conclusion 58
Chapter 5 An Adaptively Biased Stacked Power Amplifier without Output Matching Network in 90-nm CMOS 60
5.1. Architecture Survey 60
5.1.1 Structure A 60
5.1.2 Structure B 61
5.1.3 Structure C 62
5.2. Circuit Design 63
5.2.1 Core Circuit 63
5.3. Simulation and Measurement Results 74
5.4. Discussion and Conclusion 80
Chapter 6 A K-Band Transformer-based Power Amplifier with Adaptive Biasing Network 82
6.1. Architecture Survey 82
6.1.1 Wilkinson Combiner 82
6.1.2 Transmission Line Combiner 83
6.1.3 Transformer-based Combiner 83
6.2. Circuit Design 85
6.2.1 Stacked PA 85
6.2.2 Adaptively Biased Network (ABN) 91
6.2.3 Transformer Design 96
6.3. Simulation and Measurement Results of Work C and D 102
6.3.1 Work C 102
6.3.2 Work D 113
6.3.3 Discussion 125
Chapter 7 Conclusion and Future Work 127
Reference 128

[1] S. Shakib, H.-C. Park, J. Dunworth, V. Aparin and K. Entesari, "A Highly Efficient and Linear Power Amplifier for 28-GHz 5G Phased Array Radios in 28-nm CMOS," IEEE J. Solid-State Circuits, vol. VOL. 51, no. NO. 12, pp. 3020-3036, Dec. 2016.
[2] P.-H. Chen, H.-K. Chiou and Y.-C. Wang, "A K-band 24.1% PAE Wideband Unilateralized CMOS Power Amplifier Using Differential Transmission-Line Transformers in 0.18-μm CMOS," vol. VOL. 26, no. NO. 11, pp. 924-926, NOV. 2016.
[3] S. R. Helmi, J.-H. Chen and S. Mohammadi, "High-Efficiency Microwave and mm-Wave Stacked Cell CMOS SOI Power Amplifiers," IEEE Trans. Microw. Theory Techn., vol. 64, no. 7, July 2016.
[4] T.-Y. Huang, Y.-H. Lin and H. Wang, "A K-Band Adaptive-Bias Power Amplifier with Enhanced Linearizer Using 0.18-um CMOS Process," IEEE Int. Microw. Symp., pp. 1-3, May 2015.
[5] H. Alsuraisry, J.-H. Cheng, S.-J. Luo, W.-J. Lin, J.-H. Tsai and T.-W. Huang, "A 24-GHz Transformer-Based Stacked-FET Power Amplifier in 90-nm CMOS Technology," Asia-Pacific Microw. Conf., vol. 3, pp. 1-3, Dec. 2015.
[6] J. A. Jayamon, J. F. Buckwalter and P. M. Asbeck, "Multigate-Cell Stacked FET Design for Millimeter-Wave CMOS Power Amplifiers," IEEE J. Solid-State Circuits, vol. 51, no. 9, SEPTEMBER 2016.
[7] B. Razavi, RF Microelectronics, 2 ed., Prentice Hall, 2012.
[8] J. Y.-C. Liu, R. Berengure and M.-C. F. Chang, "Millimeter-Wave Self-Healing Power Amplifier With Adaptive Amplitude and Phase Linearization in 65-nm CMOS," IEEE Trans. Microw. Theory Techn., vol. 60, no. 5, May 2012.
[9] I. Aoki, S. D. Kee, D. B. Rutledge and A. Hajimiri, "Distributed Active Transformer—A New Power-Combining and Impedance-Transformation Technique," IEEE Trans. Microw. Theory Techn., vol. 50, no. 1, JANUARY 2002.
[10] H.-T. Dabag, H. Bassel, F. Golcuk, A. Agah, J. F. Buckwalter and P. M. Asbeck, "Analysis and Design of Stacked-FET Millimeter-Wave Power Amplifiers," IEEE Trans. Microw. Theory Techn., vol. 61, no. 4, APRIL 2013.
[11]Y. Kim and Y. Kwon, "Analysis and Design of Millimeter-Wave Power Amplifier Using Stacked-FET Structure," IEEE Trans. Microw. Theory Techn., vol. 63, no. 2, FEBRUARY 2015.
[12] U. Kim and Y. Kwon, "A High-Efficiency SOI CMOS Stacked-FET Power Amplifier Using Phase-Based Linearization," IEEE Microw. Compon. Lett., vol. 24, no. 12, DECEMBER 2014.
[13] H.-F. Wu, Q.-F. Cheng, X.-G. Li and H.-P. Fu, "Analysis and Design of Ultra-broadband Stacked Power Amplifier in CMOS Technology," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 63, no. 1, pp. 49-53, Jan. 2016.
[14] A. Agah, J. A. Jayamon, P. M. Asbeck, L. E. Larson and J. F. Buckwalter, "Multi-Drive Stacked-FET Power Amplifiers at 90 GHz in 45 nm SOI CMOS," IEEE J. Solid-State Circuits, vol. 49, no. 5, MAY 2014.
[15] J.-H. Chen, S. R. Helmi and S. Mohammadi, "A fully-integrated Ka-band stacked power amplifier in 45nm CMOS SOI technology," IEEE Silicon Monolithic Integr. Circuits in RF Syst., pp. 55-77, 2013.
[16] H. Koo, B. Koo and S. Hong, "Highly Efficient 24-GHz CMOS Linear Power Amplifier with Adaptive Bias Circuits," Asia-Pacific Microw. Conf., pp. 75-77, Jan. 2013.
[17] J. Y.-C. Liu, C.-T. Chan and S. S.-H. Hsu, "A K-Band Power Amplifier with Adaptive Bias in 90-nm CMOS," European Microw. Integr. Circuits Conf., pp. 432-435, Oct. 2014.
[18] H. Zhang and Q. Xue, "60-GHz CMOS Current-Combining PA With Adaptive Back-Off PAE Enhancement," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 63, no. 9, Sep. 2016.
[19] A. Agah, W. Wang, P. Asbeck, L. Larson and J. Buckwalter, "A 42 to 47-GHz, 8-bit I/Q digital-to-RF converter with 21-dBm Psat and 16% PAE in 45-nm SOI CMOS," IEEE Radio Frequency Integrated Circuits Symp., pp. 249-252, Jun. 2013.
[20] K. Kim and C. Nguyen, "Design of a K-Band Power Amplifier for High Gain, Output Power and Efficiency on 0.18-um SiGe BiCMOS Process," Asia-Pacific Microw. Conf., pp. 594-596, Nov. 2014.
[21] J.-W. Lee and B.-S. Kim, "A K-Band High-Voltage Four-Way Series-Bias Cascode Power Amplifier in 0.13 m CMOS," IEEE Microw. Compon. Lett., vol. 20, no. 7, July 2010.
[22] P. Huang, K. Guo, Y. Yu and K. Kang, "A 21.08 dBm Q-Band Power Amplifier in 90-nm CMOS Process," IEEE Int. Wireless Symp., Mar. 2014.
[23] ETSI, "Broadband Radio Access Networks (BRAN); 60 GHz Multiple-Gigabit WAS/RLAN Systems; Harmonized EN covering the essential requirements of article 3.2 of the R&TTE Directive," ETSI EN 302 567 v2.0.22, 2016.
[24] FCC, "Use of Spectrum Bands Above 24 GHz For Mobile Radio Services, et al," FCC 16-89, 2016.
[25] Y.-N. Jen, J.-H. Tsai, C.-T. Peng and T.-W. Huang, "A 20 to 24 GHz 16.8 dBm Fully Integrated Power Amplifier Using 0.18-um CMOS Process," IEEE Microw. Compon. Lett, vol. 19, no. 1, Jan. 2009.
[26] K. Joshin, Y. Kawano, M. Fujita, T. Suzuki, M. Sato and T. Hirose, "A 24 GHz 90-nm CMOS-Based Power Amplifier Module with Output Power of 20 dBm," IEEE Radio-Frequency Integration Techn., pp. 217-220, Jan. 2009.
[27] H. Koo, B. Koo and S. Hong, "Highly Efficient 24-GHz CMOS Linear Power Amplifier with an Adaptive Bias Circuit," IEEE Asia-Pacific Microw. Conf., pp. 7-9, Dec. 2012.
[28] K. Kim and C. Nguyen, "Design of a K-Band Power Amplifier for High Gain, Output Power and Efficiency on 0.18-um SiGe BiCMOS Process," IEEE Asia-Pacific Microw. Conf, pp. 594-596, Nov. 2014.
[29] S. Forst, T. Zivanovic and M. Delahoy, "ULTRA-WIDEBAND SHORT-RANGE RADARS FOR AUTOMOTIVE APPLICATIONS".