本篇論文主要為研製水平式閘極氮化鎵金氧半場效電晶體於藍寶石基板上，磊晶結構最上方為重摻雜之P型氮化鎵，其厚度分為50 nm及100 nm，黃光製程前先進行活化製程以利於基極歐姆接觸之製作，經過量測與計算，接觸電阻率分別為9.14×10-2及2.17×10-1 Ω-cm2。
本論文使用感應式耦合電漿蝕刻系統(ICP-RIE)進行氮化鎵蝕刻製程，但材料表面會因電漿蝕刻而受損，為了修復表面，本論文採用不同表面處理方式，分別為：(a) 浸泡鹽酸、BOE及硫酸等酸性溶液，(b) 以低瓦數之ICP-RIE進行化學性乾式蝕刻，(c) 以85 ℃之TMAH溶液浸泡一小時，以及(d) 在450 ℃環境下進行20次的Digital etch等方式互相搭配。
由量測結果可得，以Digital etch進行表面處理之試片擁有最佳的電性，其閾值電壓為4.21 V，最大汲極電流密度為3.61 mA/mm，計算後得到其場效遷移率為24.42 cm2/V-s。

In this study, GaN-based planar gate MOSFETs were fabricated on sapphire substrate. A heavily-doped P-type GaN layer was grown on the top of the epitaxial structure. The heavily-doped P-type GaN is with different thickness of 50 nm and 100 nm. The contact resistivity of body contact was 9.14×10-2 Ω-cm2 for 50 nm and 2.17×10-1 Ω-cm2 for 100 nm, respectively. In order to fabricate body ohmic-contact, the activation process was done before the lithography process.
The GaN-etching process was done by the inductively coupled plasma reactive ion etching system (ICP-RIE). It might cause damage to the surface of GaN because of the plasma etching process. In order to recover the surface quality, different methods of surface treatment were carried out and compared, namely: (a) soaking in hydrochloric acid, BOE and Sulfuric acid, (b) chemistry dry-etching by the low-power ICP-RIE, (c) soaking in TMAH solution at 85 ℃ for an hour, and (d) 20 cycles of digital etch at 450 ℃.
From the measurement, it was found that the best device performance was achieved with 20 cycles of digital etch at 450 ℃. With a threshold voltage of 4.21 V and a maximum drain current density of 3.61 mA/mm, the calculated field-effect mobility is 24.42 cm2/V-s.

摘要...........................I
Abstract.......................II
目錄...........................III
圖目錄.........................V
表目錄.........................VII
第一章 序論.....................1
第二章 元件介紹及實驗設計........10
第三章 光罩設計及元件製程........26
第四章 元件量測結果分析..........37
第五章 結論與未來工作............73
參考文獻........................74

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