近年來，因應可攜式消費性電子產品如智慧型手機、穿戴式裝置、平板電腦等的普及以及物聯網的需求，眾多著重於低功耗之靜態隨機存取記憶體(Static Random Access Memory, SRAM)陸續被開發。然而隨著互補式金氧半場效電晶體(CMOS)製程微縮至奈米量級，相對應之漏電流(Off-state leakage)隨之大幅上升，導致揮發性記憶體(Volatile)之靜態功耗大幅上升而成為奈米世代靜態隨機存取記憶體之主要挑戰。
近年來在傳統靜態隨機存取記憶體中，多以胞架構以及操作技巧為達到最低化功耗，其中一種代表性的方法為利用與非揮發性(Non-volatile)記憶元件如電阻式隨機存取記憶體(Resistive Random Access Memory, RRAM)以及磁阻式隨機存取記憶體(Magnetic Random Access Memory, MRAM)做結合以達到以零功耗保存資料，並同時仍保有快速獲取資料的固有特性。然而將非揮發性記憶元件新增至邏輯靜態隨機存取記憶體陣列中普遍需要額外的製程步驟或光罩，導致製程上的複雜度以及應用的彈性限制，另一方面在後段製程為主的RRAM以及MRAM需要由多層穿孔以及金屬層所組成的大型連接橋連接至SRAM，在SRAM資料儲存點產生了額外的寄生電容進而影響獲取資料的速度。
本論文首次提出一種結合淺溝槽電阻式隨機存取記憶體之新型非揮發性靜態隨機存取記憶體，相容於互補式金氧半場效電晶體邏輯製程且不需要額外光罩或特殊製程步驟，並藉由特殊之自我屏蔽資料儲存機制來達成低功耗以及快速操作的需求。藉由結合兩個淺溝槽電阻式隨機存取記憶體內嵌於SRAM結構中，資料可經由交叉耦合揮發性架構快速寫入或讀取，並可以透過自我屏蔽機制將資料非揮發式儲存於電阻式儲存點中，進而在保存資料的同時達到零靜態功耗。

In recent years, various low-power static random access memories have been developed for meeting the need in computing systems on portable devices and IOT applications. As CMOS technology scales down to nano-meter regime, the off-state leakage current increases drastically, which leads to worsen static power consumption for volatile memory modules. The static power consumption raised by the leakage current in nano-scaled transistors has become one of the key challenges for the advancement of low power SRAMs. Over the years, different cell structures or operation techniques have been proposed for minimizing power consumption in SRAMs. Some of the newly proposed cells incorporate non-volatile storage elements, such as RRAMs and MRAMs, to achieve zero-holding power while maintaining low power and fast accessing speed in processing volatile data. However adding non-volatile storage elements onto logic based SRAM arrays generally requires additional layers and/or process to the standard logic platforms. This will unavoidably increase process complexity to their development flexibilities. In addition, these back-end based RRAMs and MRAMs require large connecting structure composed of multi-stack of vias and metals to the SRAM cells. These bridging structures increase parasitic capacitance to the SRAM data storage node, affecting the accessing speed of these non-volatile SRAM cells. In this work, a new zero static-power 4T nv-SRAM with STI-sidewall RRAMs located next to the floating storage nodes of 4T SRAM has been firstly proposed and demonstrated. This 4T2R nv-SRAM features non-volatile data storage, zero holding power and fast accessing speed.

摘要 i
Abstract ii
致謝 iii
內文目錄 iv
附圖目錄 vii
附表目錄 ix
第一章 序論 1
1.1 前言 1
1.2 揮發性記憶體介紹及微縮挑戰 2
1.3 論文大綱 3
第二章 電阻式記憶體及靜態記憶體文獻回顧 9
2.1 邏輯相容內嵌式電阻式記憶體介紹 9
(a) 基本操作特性 9
(b) RRAM Model 10
(c) 邏輯相容內嵌式電阻式記憶體技術比較 11
2.2 靜態隨機存取記憶體介紹 12
(a) 靜態隨機存取記憶體 12
(b) 非揮發性靜態隨機存取記憶體介紹 12
(c) 非揮發性靜態隨機存取記憶體技術比較 13
2.3 小結 13
第三章 淺溝槽絕緣電阻式記憶體(STIRRAM) 25
3.1 淺溝槽絕緣結構簡介 25
3.2 淺溝槽絕緣電阻式記憶體製程流程 26
3.3 元件特性以及可靠度分析 27
(a) 直流與交流操作下之特性 27
(b) 可靠度量測與分析 28
3.4 小結 28
第四章 結合淺溝槽絕緣電阻式隨機存取記憶體之非揮發性靜態隨機存取記憶體 40
4.1 淺溝槽非揮發性靜態隨機存取記憶體概念 40
(a) Nv-SRAM Cell架構 40
(b) 可調變字元線電壓之初始化 41
4.2 非揮發性資料儲存 41
(a) 自我屏蔽寫入機制 41
(b) 非揮發性資料自我復原行為 42
(c) 靜態雜訊邊限及動態特性分析 42
4.3 個體變異度對靜態雜訊邊限之蒙地卡羅分析 43
(a) 個體初始化後之電阻變異 43
(b) 基於隨機電報雜訊之電阻變異 43
(c) 基於製程上之臨界電壓變異 44
4.4 非揮發-邏輯連接橋之寄生電容效應分析 45
(a) 儲存點之寄生電容比較 45
(b) 寄生電容對動態操作速度之影響 45
4.5 小結 46
第五章 總結 64
參考文獻 65

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