近年來，非揮發性記憶體被普遍地應用在許多電子產品且市場需求也日益增大，並且追求大容量、低功耗與低成本的記憶體。快閃記憶體(FLASH)是非揮發性記憶體的主流，在市面上受到歡迎且已被廣泛地使用。然而，快閃記憶體元件在製程日益微縮下遇到許多挑戰且寫入與擦除的操作需要較高的電壓以及較長的時間。因此，有一些新興的記憶體被開發用來取代快閃記憶體做為下世代非揮發性記憶體。
在新世代非揮發性記憶體中，電阻式記憶體(RRAM)是極有代表性，具有低功率、低寫入電壓及較低的面積消耗及具有CMOS邏輯製程相容性的特性。但是隨著元件微縮，RRAM也受到一些困難，例如較小的阻值比(RH/RL)及寫入時間分布較廣。這些元件特性將會讓電路設計上受到更大挑戰。RRAM元件有另外一個特別的操作不同於其它非揮發性記憶體，就是傳導路徑形成機制(FORMING)；RRAM出廠前，記憶體內所有位元皆需進行過一次FORMING操作先讓元件產生導電絲並使其阻值變低，才會將產品出廠讓客戶使用；因此，RRAM在製作過程中需花費額外的時間去切換與成本來進行FORMING操作。另一個問題是RRAM的寫入延遲時間，因為SET與RESET的寫入操作是不同時間等級的，因此寫入時間主要是被需要花較長的寫入操作(SET或RESET)給主導。
在此，我們提出自動化寫入機制來解決上述提到的問題。在記憶體中操作中，我們可以將自動化寫入機制設置為另一種模式，不同於正常的寫入模式，主要適用於大容量一次性寫完。一旦前一個細胞已被寫入成功，此時自動化寫入機制可以自動感測切換至下一個細胞的位址，可達到省時間高效率的效益。對FORMING來說，可以解決繁複的製做過程。除了有自動化地功能，我們也提出多組並行操作的架構，並與原始且最簡易的字元基礎架構做比較，我們得到隨著記憶體容量增大，自動化寫入機制可以得到更多的好處。自動化寫入機制不只可以做Auto-FORMING的功能，也可以透過不同的應用搭配Auto-SET與 Auto-RESET功能去藉此達到寫入延遲時間的減少。
將我們提出的想法以1Mb Contact-RRAM記憶體的規格實現在台積電65奈米CMOS邏輯製程上。此架構以高效率操作解決了RRAM在製造中的挑戰，且與原始架構相比，用FOM評估可減少52.9%。

Recent years, the application of non-volatile memories is common used for many electronic product and the market demand is larger, which require larger capacity, lower power and lower cost. The mainstream of non-volatile is Flash memory that is quite popular and widely used. However, Flash memory encounters more challenges in process scaling and require higher voltage to program/erase with longer write time. However, there are some emerging non-volatile memories that have developed to replace FLASH memory as next generation non-volatile memory.
Resistive random access memory (RRAM) is one of the most representative in next generation NVM with lower power, lower write voltage and lower area with CMOS logic-compatible. Nevertheless, RRAM also suffers some problem as device shrinking, such as smaller R ratio (RH/RL) and widen write time distribution. These device characteristic issues will cause challenge on design circuits. In particular, RRAM device has another special operation, FORMING, different from other NVM. Before RRAM leaving the factory, all of bits in RRAM array should be formed one time to form the filament, which make the resistance of cell be lower, and then customer could use this memory product to store the data; therefore, we need to spend additional time to switch every bit and additional cost for FORMING operation on manufacturing. The other issue is ReRAM write latency; because SET operation and RESET operation are different write timing order, the write latency is dominated by the longer operation.
Here, we proposed Auto-Write mechanism to solve above issues. Auto-Write can operate the other mode for memory, which different from the normal write mode; it is apply to write large capacity at one time. Auto-Write can automatically detect and switch to the next address of the cell once the previous cell has been written already, which could save more time to reach high efficiency. For the FORMING operation, it solve complicated operation on manufacturing. In addition to this benefit of automatic switching function, we also proposed multiple grouping in parallel operation scheme to improve write efficiency, which make the amount of improvements also increase as ReRAM density increase compare with the simplest architecture, word-based. Auto-Write scheme not only can do Auto-FORMING function but also can do Auto-SET and Auto-RESET operation with different application to achieve write latency reduction.
We implement our proposed work Auto-Write at 65nm 1Mb Contact-ReRAM memory in TSMC CMOS process. This work solves RRAM manufacturing challenge with high efficiency operation and can gain 52.9% reduction on the FOM evaluation that compare with the original architecture.

摘要 ii
Abstract iv
Contents vii
List of Figures ix
List of Tables xi
Chapter 1 Introduction 1
1.1 The Memory Landscape 1
1.1.1 RAM 3
1.1.2 CAM 3
1.1.3 ROM 4
1.1.4 Programmable NVMs 4
1.2 Challenges of Flash Memory 5
1.3 Emerging Non-Volatile Memories 8
Chapter 2 Characteristic of Contact-ReRAM 11
2.1 Structure of Contact-ReRAM 11
2.2 Switching Mechanism 12
2.3 Distribution of Contact-ReRAM 13
2.4 Read Operation 15
2.5 Write Operation 16
Chapter 3 Design Challenge 18
3.1 Design Challenge of ReRAM Write 18
3.2 Previous Work 20
3.2.1 Write Termination 21
3.2.2 Common FORMING Method 24
Chapter 4 Proposed Scheme and Analysis 27
4.1 Concept 27
4.2 Scheme and Operation 31
4.3 Analysis and Comparisons 37
Chapter 5 Measurement Result and Conclusion 42
5.1 CRRAM Macro Architecture 42
5.2 Design for Test 44
5.3 Measurement Result 46
5.4 Conclusion and Future Works 50
Reference 53

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