在電晶體隨著摩爾定律規則微縮的時代，平面架構的微縮已達到物理極限，三維度立體結構的鰭式場效電晶體在能提升閘極控制能力及降低漏電流的情況下發展出超越摩爾定律的可能性，此架構因其高微縮性已被先進製程採用作為主流架構。然而元件結構的大幅度改變也伴隨著寄生效應的增生，其條狀接觸槽及突起式源極與汲極磊晶區皆造成寄生電容的比例大幅提升，因此寄生效應對於單一元件表現的影響以及整體電路的實際效能影響，是在現今大量倚靠此元件的半導體IC產業迫切需要深入了解的重要課題。
本篇論文中先分析單一鰭式場效電晶體元件內部寄生電阻及寄生電容組成成分及所佔比例，建立出符合分析結果的三維電晶體模組。透過此模組延伸討論不同鰭數架構下的寄生效應以及針對實際製程中額外添加的虛設閘極架構探討其實際寄生電容是否會影響整體元件特性。同時除了單一元件的寄生效應外，論文也深入探討寄生效應在電路中對實際效能的影響，以靜態隨機存取記憶作為實例建構出模擬電路架構，並利用電路的基本特性曲線比較RC寄生效應對於實際電流效能所造成的差異。
針對寄生電容的萃取，本論文提出一種新穎的電容量測方法，可直接量測到單一元件的寄生電容值；有別於傳統的電容量測法，不會因為受限於量測機台的精準度而須將待測元件串接成大面積，以達到增加寄生電容至可量測級別。然而此量測方法的部分架構因受限於僅16奈米先進製程技術可使用，因此提出改良該架構提出了可適用於各製程技術的電容量測方法。

In the generation which transistors are scaled down by following the Moore's law, planar structures scalability had reached physical limits. Three-dimensional FinFET structure with its increment of gate control ability and decrement of leakage current has developed for further scaling of gate length beyond 20nm. This structure has been adopted as mainstream structure due to its highly scalability, and yet along with its massive change in the structure lead to risen parasitic effects. The slot contacts and the raised source/drain regions with expanded volume can lead to increased parasitic capacitance effect. Therefore, the parasitic effects on single device’s and overall circuit’s performance are critical issues to overall circuit performance.
In this work, first of all, components contributed to the parasitic resistance and capacitance of a single FinFET device and its ratios are extracted. A three-dimensional transistor model which fits the measurement results is built. Then through the extensive of simulation result, the parasitic effects of multi-fin structure are discussed. Also, the dummy patterns added in the manufacture process are simulated, and its effects on overall device’s performance are investigated. Lastly, the effects of parasitic RC on the overall circuit’s performance are studied using 6T-SRAM as an example. A simulated circuit and compared the parasitic effects through testing its characteristic curves.

A novel approach for the parasitic capacitance extraction of nano-scaled FinFETs is proposed in this work. Unlike traditional parasitic capacitance extractions which requires test patterns of larger area. Direct extraction of capacitance on a single device is enabled by this method. A modified test pattern is proposed for planer, lastly CMOS technology platforms.

摘要 i
Abstract ii
致謝 iv
內文目錄 vi
附圖目錄 ix
附表目錄 xi
第一章 序論 1
1.1 鰭式場效電晶體之介紹 1
1.2 研究動機 2
1.3 論文大綱 3
第二章 鰭式場效電晶體寄生效應 4
2.1 單鰭式場效電晶體細部寄生電阻萃取分析 4
(a)通道調變寄生電阻萃取法 4
(b)細部電阻萃取分析 5
2.2 單鰭式場效電晶體細部寄生電容萃取 6
2.2.1條狀接觸槽耦合之浮動閘極架構寄生電容萃取法 6
2.2.2細部電容萃取分析 7
2.3 單鰭式場效電晶體模組建構介紹 8
2.3.1模擬環境及電晶體架構介紹 8
2.3.2 基本電性分析 9
2.4 多鰭式場效電晶體的寄生電容及電阻效應 9
2.4.1 架構介紹 10
2.4.2 模擬結果分析 10
2.5 虛設閘極架構的寄生電容效應 11
2.5.1 架構介紹 11
2.5.2 模擬結果分析 12
2.6 小結 13
第三章 鰭式場效電晶體寄生效應於電路效能的影響 28
3.1 寄生效應對電路的影響分析 28
3.2 模擬環境介紹 29
3.3 靜態隨機存取記憶體介紹 29
3.3.1 虛設閘極架構的靜態隨機存取記憶體 30
3.4寄生效應下之基本特性 31
3.4.1 SNM分析 31
3.4.2 動態讀取穩定性分析 32
3.5小結 32
第四章 萃取細部寄生電容方法之改良 41
4.1 歧異耦合之浮動閘極架構細部電容萃取原理 41
4.1.1 條狀接觸槽耦合方法 42
4.1.2 N井耦合方法 43
4.2量測環境 44
4.3 電荷式電容量測方法 45
4.3.1原理簡介 45
4.3.2 量測結果分析 46
4.4 N井耦合方法之細部電容萃取 47
4.4.1 原理介紹 47
4.4.2 細部電容萃取結果分析 48
4.5小結 49
第五章 總結 63
5.1 各類電容量測法之比較 63
5.2 結語與未來展望 63
參考文獻 65

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