晶圓在電漿製程時，暴露的金屬線如同一根根天線將會收集電荷並導致電位升高，而過高的電位將使得氧化層被擊穿導致元件特性異常，此現象稱之為電漿充電損害或天線效應。傳統偵測天線效應方法很多，像依時性介電層崩潰測試(Time dependent dielectric breakdown, TDDB)、掃描崩潰電壓(Ramp breakdown voltage)、閘極漏電流測試(Gate leakage current)等等。但這些測試方法除了有耗時、靈敏度不高等等缺點之外，也無法直接地得知電漿感應電荷之極性。
CMOS製程跟隨著摩爾定律不停的演進，元件尺寸不斷微縮，其漏電問題越趨嚴重。為了解決漏電以及功耗等等問題，全新元件結構鰭式場效電晶體(FinField-effect transistor, FinFET)被視作最好的替代元件。鰭式場效電晶體與傳統元件之最大區別在於前者為立體式閘極包覆結構，而後者則為平面式閘極。透過環繞式閘極來提升閘極控制能力，使得通道更容易受到控制並達成完全空乏，藉此大幅降低關閉電流，在速度或是功耗均有明顯的優勢。
此篇論文進行應用於FinFET製程之電容耦合浮動閘極偵測天線效應之研究。在電漿製程中，大片的金屬層所收集到的電荷透過耦合電壓的方式至浮動閘極上，而此電壓將使得基底的電荷穿隧進入浮動閘極。此方式可將電漿充電損害定性且定量的紀錄於偵測元件之中。最後只需透過簡易的電性量測讀取其臨界電壓值即可還原得知電漿損害之極性與程度。然而，由於此浮動閘極之結構在偵測單層金屬層之天線效應時，所偵測之結果可能會受到正負相消的效應，使得無法得知元件受到電漿充電損害最嚴重的情況。因此將稍對新型電漿充電損害記錄元件進行改良，提出一電漿充電具電荷分離紀錄之元件，分別記錄天線上電漿充電電荷之總正電荷量與負電荷量，藉此得知電漿充電損害最嚴重的受損情形。除此之外，論文還討論了一個偵測中段製程(MEOL)之特殊結構，幫助製程人員了解電漿製程中MEOL的損害情形。以上之記錄元件無論對於先進製程的優化以及可靠度之分析都能有正向的幫助。

As CMOS processes follows the Moore's Law, device size continues to shrink, the leakage problem becomes more serious. In order to solve the problem of leakage and power consumption, etc., FinFET is considered the best alternative devices. The biggest difference between the FinFETs and the MOSFET is that the former is a three-dimensional gate cladding structure, while the latter is a planar gate. The surrounding gate to enhances the gate control capability, making the channel more easily controlled and increasing the depletion region, so that off-state of leakage will be significantly reduced.
In IC manufacturing, plasma process is critical for achieving fine feature size and high aspect ratio structures. During the plasma process, the exposed metal wire as an antenna will collect charge and rise up the potential, then the highly potential will make the oxide layer breakdown causing abnormal component characteristics, this phenomenon is called plasma induce damage or antenna effect. Conventionally, there are many ways to detect plasma induce damage, such as time dependent dielectric breakdown, ramp breakdown voltage, gate leakage current, and so on. However, these test methods are not only time consuming, and low sensitivity, and fail to provide detail plasma charging situation.
In this paper, we apply the capacitive coupling floating gate to detect plasma charge damage in FinFET process. During the plasma process, the charge collected by the large metal layer and couple the voltage to the floating gate, leading to electron inject into or eject out of the floating gate. This method allows the damages to be qualitatively and quantitatively recorded in the recorder. Finally, by a simple electrical measurement to read the threshold voltage, we can know the polarity and degree of plasma damage. However, by QFG detection of the antenna effect, the detected result may be subject to charge neutralization, which causes that we can’t detect the most serious situation of the plasma charge damage. Therefore, we slightly improved the new type recorder, and propose the charge splitting in-situ recorder to independently detect ion charging and electron charging effects. In addition, we have proposed a special structure to detect the middle-end-of- line process (MEOL), to help process personnel to understand the plasma damages in MEOL. The new structures provide powerful assistance for process optimization and reliability evaluations.

摘要------------------------------------i
Abstract----------------------------- iii
致謝------------------------------------v
內文目錄------------------------------- vi
附圖目錄------------------------------viii
附表目錄---------------------------------x
第一章 序論----------------------------1
1.1 電漿充電損害簡介-----------------2
1.2 研究動機-------------------------3
1.3 論文大綱-------------------------4
第二章 電漿充電損害偵測元件回顧----------6
2.1 傳統電漿充電損害偵測方法回顧------6
2.1.1 元件基本參數偵測------------------6
2.1.2 閘極漏電流測試--------------------7
2.1.3 介電質崩潰電壓掃描測試-------------7
2.1.4 時間相依介電質崩潰測試-------------8
2.1.5 零時介電質崩潰測試-----------------8
2.1.6 電容-電壓測試---------------------9
2.2 新型電漿充電損害記錄元件----------9
2.2.1 元件結構介紹----------------------9
2.2.2 操作機制與原理--------------------11
2.3 小結----------------------------12
第三章 元件模型建立---------------------20
3.1 電漿充電機制及模型回顧------------20
3.2 元件模型與模擬分析----------------21
3.2.1 元件模型流程介紹-------------------21
3.2.2 元件模型模擬結果-------------------22
3.3 小結-----------------------------22
第四章 電漿充電損害偵測元件量測分析結果----30
4.1 量測環境與儀器設置-----------------30
4.2 新型電漿充電損害記錄元件------------31
4.2.1 基本讀取特性------------------------31
4.2.2 天線效應飽和之影響------------------31
4.2.3 天線電壓之影響----------------------32
4.2.4 天線幾何圖案之效應-------------------33
4.2.5 P型與N型紀錄元件比較-----------------33
4.3 偵測中段製程之N型井耦合結構---------34
4.4 過蝕刻效應分析---------------------35
4.5 小結------------------------------35
第五章 電漿充電具電荷分離紀錄之元件--------57
5.1 元件概念與結構簡介--------------------58
5.2 電性模擬結果--------------------------58
5.3 電荷分離之量測結果--------------------59
5.4 電荷分離紀錄元件之資料儲存性-----------60
5.5 小結------------------------------61
第六章 總結------------------------------75
6.1 新型紀錄元件與傳統偵測方法之比較--------75
6.2 結語與未來展望------------------------76
參考文獻-----------------------------------78

[1] K. Eriguchi, Y. Takao, and K. Ono, “A New Aspect of Plasma-Induced Physical Damage in Three-Dimensional Scaled Structures,” IEEE Internationl Conference on IC Design & Technology, pp.1-5, May 2014.
[2] A. Matsuda, Y. Nakakubo, Y. Takao, K. Eriguchi and K. Ono, “Atomistic Simulations of Plasma Process-Induced Si Substrate Damage”, Internationl Conference on IC Design & Technology, pp.191-194, May 2013.
[3] P. Simon and W. Maly, “Identification of plasma-induced damage conditions in VLSI designs,” Semiconductor Manufacturing, IEEE Transactions on , vol.13, no.2, pp.136,144, May 2000.
[4] H. C. Shin and C. Hu, “Thin gate oxide damage due to plasma processing”, Semicond. Sci. Technol. vol. 11, (1996). p463.
[5] F. F. Chen, “Plasma-Induced Oxide Damage: A Status Report”, Department of Electrical Engineering, UCLA, Oct 1996.
[6] Z. Wang, “Detection of and protection against plasma charging damage in modern IC technologies”, PhD Thesis, 2004, ISBN 90-365-2079-7.
[7] Z. Wang, J. Ackaert, A. Scarpa, C. Salm, F. G. Kuper and M. Vugts, “Strategies to cope with plasma charging damage in design and layout phases,” Integrated Circuit Design and Technology, 2005. ICICDT 2005, pp.91,98, 9-11 May 2005.
[8] J. P. McVittie, “Process charging in ULSI: mechanisms, impact and solutions,” Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International, pp.433,436, 10-10, Dec 1997.
[9] W. H. Choi, P. Jain and C. H. Kim, “An array-based circuit for characterizing latent Plasma-Induced Damage,” Reliability Physics Symposium (IRPS), 2013 IEEE International, pp.4A.3.1,4A.3.4, 14-18 Apr 2013.
[10] Z. Wang, P. Tanner, C. Salm, T. Mouthaan, F. Kuper, M. Andriesse and E. van der Drift, “Plasma-Induced Charging Damage of Gate Oxides” STW, Mierlo, pp.593, 1999.
[11] C. Gabriel, K. Elliott, D. Kwong, and A. Ray, “Charge buildup damage to gate oxide,” in Proc. SPIE, vol. 2091, pp.239-247, 1994
[12] A. Martin, “Review on the Reliability Characterisation of Plasma-Induced Damage, ” J. Vac. Sci. Technol. B, 27(1), pp.426–434, 2009.
[13] K. Eriguchi, M. Kamei, Y. Takao and K. Ono, “High-k MOSFET performance degradation by plasma process-induced charging damage — Impacts on device parameter variation,” Integrated Reliability Workshop Final Report (IRW), 2012 IEEE International , pp.80,84, 14-18 Oct 2012.
[14] P.J. Liao, S.H. Liang, H.Y. Lin, J.H. Lee, Y. Lee, J.R. Shih, S.H. Gao, S.E. Liu and K. Wu, “Physical origins of plasma damage and its process/gate area effects on high-k metal gate technology,” Reliability Physics Symposium (IRPS), 2013 IEEE International , pp.4C.3.1,4C.3.5, 14-18 Apr 2013.
[15] C.D. Young, G. Bersuker, F. Zhu, K. Matthews, R. Choi, S. C. Song, H. K. Park, J. C. Lee and B. H. Lee, “Comparison of Plasma-Induced Damage in SiO2/TiN and HfO2/TiN Gate Stacks,” Reliability physics symposium, 2007. proceedings. 45th annual. ieee international , pp.67,70, 15-19 Apr 2007.
[16] K. Eriguchi and K. Ono, “Quantitative and comparative characterizations of plasma process-induced damage in advanced metal–oxide– semiconductor devices,” J. Phys. D, Appl. Phys., vol. 41, no. 2, p.024 002, Jan 2008.
[17] K. S. Min, C. Y. Kang, O. S.Yoo, B. J. Park, S. W. Kim, C. D. Young, D. Heh, G. Bersuker, B. H. Lee and G. Y. Yeom, “Plasma induced damage of aggressively scaled gate dielectric (EOT ≪ 1.0nm) in metal gate/high-k dielectric CMOSFETs,” Reliability Physics Symposium, 2008. IRPS 2008. IEEE International , pp.723,724, April 27 2008-May 1 2008.
[18] V. Velayudhan, J. Martin-Martinez, M. Porti, C. Couso, R. Rodriguez, M. Nafria, X. Aymerich, C. Marquez, F. Gamiz, “Threshold voltage and on-current Variability related to Interface Traps Spatial Distribution, ” European Solid State Device Research Conference(ESSDERC), pp.230–233, Sept 2015.
[19] W. Cao, J. Kang, W. Liu, and K. Banerjee, “A Compact Current–Voltage Model for 2D Semiconductor Based Field-Effect Transistors Considering Interface Traps, Mobility Degradation, and Inefficient Doping Effect,” IEEE Transactions on Electron Devices, vol. 61, no. 12, pp.4282-4290, Dec 2014.
[20] T. Brozek, Y. D. Chan and C. R. Viswanathan, “Threshold Voltage Degradation in Plasmadamaged CMOS Transistors - Role of Electron and Hole Traps Related to Charging Damage,” European Symposium on Reliability of Electron Devices, Failure Physics and Analysis , pp.1627-1630 Oct 1996.
[21] K. P. Cheung, "Advanced plasma and advanced gate dielectric - a charging damage prospective," Reliability Physics Symposium Proceedings, 2006. 44th Annual., IEEE International , vol., no., pp.360,364, 26-30 Mar 2006.
[22] C. C. Chen, H. C. Lin, C. Y. Chang, M. S. Liang, C. H. Chien, S. K. Hsien, T. Y. Huang, T. S. Chao, "Plasma-induced charging damage in ultrathin (3-nm) gate oxides," Electron Devices, IEEE Transactions on , vol.47, no.7, pp.1355,1360, Jul 2000.
[23] N. Rahim, E. Y. Wu and D. Misra, “Investigation of Progressive Breakdown and non-Weibull Failure Distribution of High-k and SiO2 Dielectric by Ramp Voltage Stress,” International Reliability Physics Symposium, pp.GD.2.1-GD.2.6 Apr 2011.
[24] T. B. Hook, D. Harmon, C. Lin, “Detection of thin oxide (3.5 nm) dielectric degradation due to charging damage by rapid-ramp breakdown,” Reliability Physics Symposium, 2000. Proceedings. 38th Annual 2000 IEEE International, vol., no., pp.377,388, 2000.
[25] P. C. Feijoo, T. Kauerauf, M. Toledano-Luque, M. Togo, E. San Andres and G. Groeseneken, "Time-Dependent Dielectric Breakdown on Subnanometer EOT nMOS FinFETs," IEEE Transactions on Device and Materials Reliability, , vol.12, no.1, pp.166-170, Jan 2012.
[26] H. J. Lee, and K. K. Kim, "Analysis of Time Dependent Dielectric Breakdown in Nanoscale CMOS Circuits," International SoC Design Conference , pp.440-443, Nov 2011.
[27] S. Ma, W. L. N. Abdel-Ati, and J. P. McVittie "Sensitivity and limitations of plasma charging damage measurements using MOS capacitors structures," Electron Device Letters, IEEE , vol.18, no.9, pp.420,422, Sept 1997.
[28] R. G. Forbes, "A more scientific approach to describing Fowler-Nordheim theory," International Vacuum Nanoelectronics Conference (IVNC), pp.66-67, Jul 2015.
[29] B. Rumberg and D. W. Graham, "Efficiency and reliability of Fowler-Nordheim tunnelling in CMOS floating-gate transistors," Electronics Letters , vol.49, no.23, pp.1484-1486, Dec 2013.
[30] R. K. Ellis, "Fowler-Nordheim Emission from Non-planar Surfaces," IEEE Electron Device Letters, vol.3, no.11, pp.330-332, Nov 1982.
[31] W. H. Lee, and M. J. Chen, " Gate Direct Tunneling Current in Uniaxially Compressive Strained nMOSFETs: A Sensitive Measure of Electron Piezo Effective Mass," IEEE Transactions on Electron Devices, vol.58, no.1, pp.39-45, Nov 2011.
[32] S. H. Lo, D. A. Buchanan and Y. Taur, "Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides," IBM Journal of Research and Development, vol.43, no.3, pp.27-337, May 1999.
[33] G. Chakraborty and C. K. Sarkar, " Study of Direct tunneling current in Carbon nanotube based Floating gate devices," International Workshop on Physics of Semiconductor Devices, pp.872-875, Dec 2007.
[34] K. F. You, M. C. Chang, and C. Y. Wu, "A New Simulation Model for Plasma Ashing Process-Induced Oxide Degradation in MOSFET," IEEE Transactions on Electron Devices, vol.45, no.1, pp.239-246, Jan 1998.