隨著電子產品持續縮小，追求高速、高腳數等需求，傳統的打線封裝已經逐漸不適用，能應用的範圍也大多為較低階之產品，本研究以覆晶封裝技術開發出960*540微型發光二極體陣列之圖像顯示為目的，藉由覆晶封裝高速、縮小體積、高腳數(I/O)、散熱佳等優點，應用於微型二極體陣列，找出最佳的製程及封裝條件，使每一像素都能發光，擁有良好良率與均勻性。
本研究以銦為接合材料，以電子束蒸鍍直徑6um高4um之銦凸塊，藉由串聯迴路之菊輪狀結構量測其電阻，模擬覆晶型微型發光二極體之接合狀況，測試出單條迴路之電阻585Ω，以此實驗手法套用至960*540微型發光二極體陣列之覆晶封裝，最終完成一覆晶型960*540微型發光二極體陣列，其良率為85.51%，藉由此研究結果，未來應用於無光照微影、攜帶式微型投影器、穿戴式裝置，擴展微型發光二極體應用程度及其價值。

With the continuous reduction of electronic products, the pursuit of high-speed, high input/output (I/O) counts, and other needs, traditional wire bonding has been gradually not applicable. The scope of the product that packed by wire bonding is also lower. This study is to developed packing of 960 * 540 Micro light emitting diode (LED) array by flip chip bonding technology for the purpose of the display. With the advantage of flip-chip bonding like high-speed, reduced size, high number I / O, good heat dissipation, and so on. It is used in micro LED array and find the best bonding conditions, so each pixel can be lightened with good yield and uniformity.
We use indium as the interconnection material in this research. We evaporate indium bump by E-gun with 6μm of diameter and 4μm of height. Daisy chain is used to measure the resistance of the structure and simulate the condition of LED bonding. Test the single loop resistance and apply the condition to flip chip bonding of 960*540 micro LED array. Finally, make a micro display with the yield rate of 85.51%. With the results of this research, it can be applied in mask-free lithography, head mounted display, and wearable device to increase the value and application of micro LED.

摘 要 i
Abstract ii
致謝 iii
Contents iv
List of Figures v
List of Tables vii
Chapter 1 Introduction 1
1-1 Introduction to flip chip technology 1
1-2 Introduction to Light Emitting Diodes 2
1-3 Motivation 4
Chapter 2. Backgrounds 5
2-1 Flip chip bonding 5
2-2 Under bump metallization 7
2-3 Solder bump 8
2-4 Theory of Light Emitting Diodes 13
Chapter 3. Experimental procedure 15
3-1 Daisy Chain Mask Design and Device Structure 15
3-2 Micro LED array bonding submount Mask Design and Device Structure 24
3-3 960*540 Micro LED experience process 26
Chapter 4. Results and discussions 35
4-1 Daisy chain measurement 35
4-2 Micro LED array characteristic measurement 44
4-2-3 Micro LED array I-V characteristic with new design 53
4-3 Electroluminescence (EL) spectrum of micro LED 56
4-4 Yield rate of micro LED array 58
Chapter 5. Conclusions 63
References 64

1.https://en.wikipedia.org/wiki/Indium
2.http://www.finetechusa.com/bonders/products/fineplacerr-lambda.html
3.https://en.wikipedia.org/wiki/Flip_chip
4.Chao-Chyun An, Ming-Hsien Wu, Yu-Wei Huang, Tai-Hong Chen, Chia-Hsin Chao, Wen-Yung Yeh “Study on Flip Chip Assembly of High Density Micro-LED Array” in 6th Int. Microsyst., Packag., Assembly, Circuits Technol. Conf. (IMPACT), pp. 336-338, October 2011.
5.Elenius, P., Levine,L, “Comparing Flip-Chip and Wire-Bond Interconnection Technologies”. Chip Scale Review, 2000.
6.https://en.wikipedia.org/wiki/Wire_bonding
7.http://www.epakelectronics.com/spt_capillaries_bsob.htm
8.Jittinorasett, S.,“UBM Formation on Single Die Dice for Flip Chip Applications”, in Department of Electrical Engineering. 1999, Virginia Polytechnic Institute and State University: Blacksburg, Virginia
9.Jon-Claude Leger, “Thermo-mechanical reliability and electrical performance of indium interconnects and under bump metallization”. B.S., Mechanical Engineering, University of New Mexico,2015
10.Indium Corporation. Physical Constants of Pure Indium. 2015, http://www.indium.com/metals/indium/physical-constants/
11.http://hyperphysics.phy-astr.gsu.edu/hbase/solids/pnjun2.html
12.http://www.ledsmagazine.com/articles/2004/01/terminology-led-efficiency.html
13.E. Fred Schubert, “Light-Emitting Diodes”, 2nd ed,CAMBRIDGE,2006, chapter 8.
14.Thompson G.H.B., “Physics of semiconductor laser devices” New York, pp.572(1980)
15.S. Cihangir and S. Kwan, “Characterization of Indium and Solder Bump Bonding for Pixel Detectors” Nuclear. Instrument and Methods in Physics Research A476 (2002) 670-675
16.Satoru Wakiyama, Hiroshi Ozaki, Yoshihiro Nabe, Tomomi Kume, Takayuki Ezaki, and Tohru Ogawa“ Novel Low-Temperature CoC Interconnection Technology for Multichip LSI (MCL) ” in Proc. IEEE 57th ECTC, 2007, pp. 610–615.
17.J. Kim, H. Schoeller, J. Cho, and S. Park, "Effect of oxidation on indium solderability", J. Electron. Mater., Vol. 37, pp. 483-489, 2008.
18.Suzuki, M, T. Uenoyama, A. Yanase, First-principles calculations of effective-mass parameters of AlN and GaN, Phys. Rev. B 52, 11 (1995), 8132-8139
19.https://www.researchgate.net/publication/234992142_Gate-controlled_spin_splitting_in_GaNAIN_quantum_wells